Ex Parte Arimilli et al

Patent Trial and Appeal Board

Oct 16, 2018

12024169 (P.T.A.B. Oct. 16, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/024,169 02/01/2008
124677 7590 10/18/2018
Russell Ng PLLC (IBM AUS)
8729 Shoal Creek Blvd., Suite 100
Austin, TX 78757
FIRST NAMED INVENTOR
Lakshminarayana B. Arimilli
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AUS920070369US 1 8779
EXAMINER
KHAKHAR, NIRA V K
ART UNIT PAPER NUMBER
2167
NOTIFICATION DATE DELIVERY MODE
10/18/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
s tephanie@russellnglaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LAKSHMINARA Y ANA B. ARIMILLI, RA VIK. ARIMILLI,
GUY L. GUTHRIE, and WILLIAM J. STARKE
Appeal 2017-002641 1
Application 12/024,1692
Technology Center 2100
Before MURRIEL E. CRAWFORD, ANTON W. PETTING, and
NINA L. MEDLOCK, Administrative Patent Judges.
MEDLOCK, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claims 13-17. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
1 Our decision references Appellants' Appeal Brief ("App. Br.," filed
March 2, 2016) and Reply Brief ("Reply Br.," filed December 6, 2016), and
the Examiner's Answer ("Ans.," mailed November 3, 2016) and Final Office
Action ("Final Act.," mailed December 21, 2015).
2 Appellants identify IBM Corporation as the real party in interest. App.
Br. 3.
Appeal2017-002641
Application 12/024,169
CLAIMED INVENTION
Appellants' claimed invention "relates to multiprocessor systems in
general, and in particular to memory controllers for multiprocessor systems"
(Spec. 1, 11. 26-27).
Claim 13, reproduced below, is the sole independent claim, and
representative of the claimed subject matter:
13. A multiprocessor system comprising:
a system memory includes a plurality of data blocks each
having a lock control section and a data section such that lock
control information and data are available via a single access;
a plurality of processing units coupled to said system
memory;
a hardware memory controller located externally from said
system memory, wherein said hardware memory controller
includes a processing unit tracking table having a plurality of
entries, wherein each entry includes a processing unit number,
and a number for indicating a relative distance of a processing
unit with said processing unit number located from said memory
controller, in response to a request for accessing one of said data
blocks by one of said plurality of processing units,
accesses said one data block directly to determine
whether or not said lock control section within said one
data block has been set;
in a determination that said lock control section
within said one data block has been set, disallows said one
processing unit to access said one data block; and
in a determination that said lock control section
within said one data block has not been set, sets said lock
control section within said one data block and allows said
one processing unit to access said one data block.
REJECTION
Claims 13-17 are rejected under 35 U.S.C. § 103(a) as unpatentable
over Wang (US 5,263,155, iss. Nov. 16, 1993), Fandrich et al.
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Appeal2017-002641
Application 12/024,169
(US 5,592,641, iss. Jan. 7, 1997) (hereinafter "Fandrich"), and
Nijhawan et al. (US 2007/0214333 Al, pub. Sept. 13, 2007) (hereinafter
"Nijhawan").
ANALYSIS
We are persuaded by Appellants' argument that the Examiner erred in
rejecting independent claim 13 under 35 U.S.C. § I03(a) because Fandrich,
on which the Examiner relies, does not disclose or suggest "a system
memory includ[ing] a plurality of data blocks each having a lock control
section and a data section such that lock control information and data are
available via a single access," as recited in claim 13 (App. Br. 5; see also
Reply Br. 2).
Fandrich is directed to a method and apparatus for selectively
enabling and disabling write access to flash blocks in a flash memory device
(Fandrich, Abstract), and discloses, with reference to Figure 3, that the flash
memory device comprises, inter alia, flash cell array 20, interface circuit 40,
and flash array controller 50 (id. col. 3, 11. 45--47). Figure 4 is a block
diagram of interface circuit 40, which comprises, inter alia, a set of block
status registers ("BSR") 216 (id. col. 6, 1. 66 - col. 7, 1. 2), i.e., one for each
of the flash cell blocks of the flash array (id. col. 7, 11. 17-20). Fandrich
discloses, at column 7, lines 43-59, cited by the Examiner, that in one
embodiment, bit 6 of each block status register in BSR 216 is a block
enabled flag indicating that the corresponding flash cell block is locked;
Fandrich also discloses in this same section, with reference of Figure 5a, that
"[ e Jach flash cell block BLOCK 0--7 is comprised of a block data area and a
block status area."
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Appeal2017-002641
Application 12/024,169
Referring to Figure 5a and the discussion at column 7, lines 43
through 59 of Fandrich, the Examiner takes the position that Fandrich
discloses a single byte (i.e., 8 bits) of data that contain seven bits of usable
data and a single bit designated as a lock flag; that stored data is typically
read at least one entire byte at a time; and that both usable data and the lock
flag bit would, therefore, be available via a single access (Ans. 7-8; see also
Final Act. 4--5), e.g., by accessing/reading a single data byte.
The difficulty with the Examiner's analysis, as Appellants point out, is
that Fandrich discloses, in Figure 5a, that flash array 20 comprises separate
block data and block status areas. The block data area, as shown in the
figure, is accessed by a block data row decoder 120 while the block status
area is accessed by a block status row decoder 122 (Reply Br. 2). In other
words, the block lock information and the block data are accessed by two
separate row decoders; as such, Fandrich's lock control information and data
are not available via a single access, as called in claim 13.
In view of the foregoing, we do not sustain the Examiner's rejection
of claim 13 under 35 U.S.C. § 103(a). For the same reasons, we also do not
sustain the Examiner's rejection of dependent claims 14--17.
Cf In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992) ("dependent claims
are nonobvious if the independent claims from which they depend are
nonobvious").
DECISION
The Examiner's rejection of claims 13-17 under 35 U.S.C. § 103(a) is
reversed.
REVERSED
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