Ex Parte 7636274 et al

Patent Trial and Appeal Board

Jan 16, 2014

95001337 (P.T.A.B. Jan. 16, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,337 06/04/2010 7636274 043326-000-0020 4959
79141 7590 01/16/2014
The Law Office of Jamie Zheng, Ph.D Esq.
P.O. Box 60573
Palo Alto, CA 94306
EXAMINER
PEIKARI, BEHZAD
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
01/16/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

INPHI CORPORATION
Requester and Appellant

v.

NETLIST, INC.
Patent Owner and Respondent
____________

Appeal 2013-009044
Inter partes Reexamination Control 95/001,337
United States Patent 7,636,274 B2
Technology Center 3900
____________

Before JOHN A. JEFFERY, KEVIN F. TURNER, and
STANLEY M. WEINBERG, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

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DECISION ON APPEAL
Third Party Requester Inphi Corporation (“Requester”) appeals under
35 U.S.C. §§ 134(b) and 315(b) the Examiner’s decision declining to adopt
Requester’s proposed rejections of claims 1-104.1 App. Br. 2.2 The
Respondent, Patent Owner Netlist (“Patent Owner”), is a party to this appeal
under 35 U.S.C. § 315(a) and disputes Requester’s contentions.
We have jurisdiction under 35 U.S.C. §§ 134 and 315, and we heard
the appeal on November 20, 2013. We affirm-in-part.

STATEMENT OF THE CASE
This proceeding arose from a request for inter partes reexamination
filed on behalf of Requester, on May 8, 2010, of United States Patent
7,636,274 B2 (“the ’274 patent”), issued to Solomon et al. on December 22,
2009.

1 Although the Claims Appendix of Requester’s Brief omits claim 81, the
Examiner’s not rejecting that claim is nonetheless appealed—a point that
was clarified at the oral hearing. See Oral Hn’g Transcript filed Dec. 13,
2013, at 16 (“Tr.”). Accordingly, we treat this omission as harmless error.
2 Throughout this opinion, we refer to (1) the Request filed May 8, 2010
(“Request”); (2) the Right of Appeal Notice mailed June 22, 2012 (“RAN”);
(3) Requester’s Appeal Brief filed September 24, 2012 (“App. Br.”); (4)
Patent Owner Respondent’s Brief filed October 25, 2012 (“Resp. Br.”); (5)
the Examiner’s Answer mailed April 16, 2013 (“Ans.”) (incorporating the
RAN by reference); and (6) Requester’s Rebuttal Brief filed May 16, 2013
(“Reb. Br.”).
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In this proceeding, the Examiner deemed claims 1-1043 to be
patentable, and declined to adopt various proposed rejections of these
claims—a decision that Requester appeals. App. Br. 2; Resp. Br. 1.

RELATED PROCEEDINGS
This appeal is said to be related to various pending proceedings. First,
US Patent 7,532,537, which is said to be a parent of the ’274 patent, is in
reexamination (Control No. 95/001,381) and on appeal to this Board
(Appeal No. 2013-009066). Resp. Br. 1.
Second, the ’274 patent and two other US patents, 7,619,912 and
7,532,537, are said to be at issue in pending stayed litigation. App. Br. 1
(citing Case No. 2:09-cv-06900 (C.D. Cal.)).
Third, we are informed that the ’274 patent, which is said to be a
continuation-in-part of US Patent 7,289,386, is the subject of pending
litigation that was stayed in connection with an associated reexamination
(Control No. 95/000,546) that was merged with another reexamination
proceeding of the ’386 patent (Control No. 95/000,577). App. Br. 1 (citing
Case No. 4:08-cv-04144 (N.D. Cal.)).
Fourth, the ’912 patent, which is said to be a continuation of the ’386
patent, is also said to be (1) the subject of pending stayed litigation, and (2)
associated with three merged reexaminations (Control Nos. 95/000,579,
95/000,578, 95/001,339). App. Br. 1-2 (citing Case No. 4:09-cv-05718
(N.D. Cal.)).

3 These claims include the ‘274 patent’s claims 1-97 (some of which were
amended during prosecution of this reexamination) and claims 98-104 that
were added during prosecution. RAN 2-3.
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Lastly, we are informed that US Patent 7,532,537, which is said to be
related to the ’274 patent, is currently being reexamined. Resp. Br. 1 (citing
Control No. 90/001,758).

THE INVENTION
The invention of the ’274 patent relates to computer system memory
modules and, specifically, improving the modules’ performance and/or
memory capacity. To this end, a memory module comprises plural memory
devices electrically coupled to a circuit that (1) selectively isolates one or
more loads of the memory devices from the computer system, and (2)
translates between a system memory domain of the computer system and a
physical memory domain of the memory module. See generally ’274 patent,
col. 1, ll. 28-32; col. 2, l. 62 – col. 3, l. 35; Figs. 1-9B. Claim 1 is illustrative
of the invention and reproduced below:
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THE PRIOR ART
The following prior art references are cited in the proposed rejections
that are at issue in this appeal:

First Named Inventor Patent or Publication Number
Publication or Issue
Date
Wong et al.
(“Wong”)
US 6,414,868 B1 July 2, 2002
Dell et al.
(“Dell”)
US 6,446,184 B2 Sept. 3, 2002
Karabatsos US 6,446,158 B1 Sept. 3, 2002
Kazuo Takeda
(“Kazuo”)4
JP 10-320270 A Dec. 4, 1998

4 Although the parties and the Examiner refer to this reference as “Kazuo,”
this is actually the first name of the inventor “Kazuo Takeda.” Nevertheless,
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QBM Alliance, Quad Band Memory (QBMTM): DDR 200/266/333 devices
producing DDR 400/533/667, Platform Conference (2002) (“QBMA”)

DESIGN SPECIFICATION FOR JEDEC DIMM STANDARD NO. 21-C, Rev. 1.3,
Release 11 b (2002) (“JEDEC”)

THE PROPOSED REJECTIONS ON APPEAL5
Requester appeals the following proposed rejections that the Examiner
did not adopt:

Claims
Statutory
Basis
(35 U.S.C.)
Cited References
1, 4-17, 23, 28-30, 32-34,
396-41, 44-47, 54-61, 63-
66, 69, 74-76, 79, 84-86,
88, 89,7 94-96
§ 103 QBMA and JEDEC (“Issue 2”)8

we adopt the parties’ and the Examiner’s nomenclature for clarity and
consistency.
5 Although Patent Owner asks that we not admit portions of the
“Background Of The Technology” section of Requester’s brief that are said
to constitute unsubstantiated statements (Resp. Br. 20)—an allegation that is
disputed (Reb. Br. 5-6)—we nonetheless consider Requester’s brief as filed,
giving any content—substantiated or otherwise—its due weight in arriving
at our decision.
6 We note a typographical error in lines 21 and 22 of claim 39 in the claims
appendix of Requester’s brief. For clarity, we presume that the term “y tem”
is intended to be “system.”
7 Although Requester omits claims 88 and 89 from the claims associated
with this proposed rejection (App. Br. 6) and Patent Owner accepts this
listing (Resp. Br. 5), the Examiner nonetheless includes claims 88 and 89 in
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1-3, 18-22, 24-28, 31, 35-
39, 42, 43, 48-53, 56, 62,
67, 68, 70-73, 84, 87
§ 103 QBMA and Dell (“Issue 3”)
1-14, 16-21, 23-48, 50-53,
55-64, 66-94, 96, 97 § 103
Wong and Karabatsos
(“Issue 6”)
1-6, 8-14, 16, 18-46, 48-64,
67-97 § 103
Dell and Karabatsos
(“Issue 7”)
98-104 § 103 QBMA and Dell (“Issue 8”)
98-104 § 103 Karabatsos and Dell (“Issue 9”)
98-104 § 103 QBMA, Dell, and Kazuo (“Issue 10”)
98-104 § 103 Karabatsos, Dell, and Kazuo (“Issue 11”)
98-104 § 103 Wong, Karabatsos, and Kazuo (“Issue 12”)

THE PROPOSED REJECTION OVER QBMA AND JEDEC (“ISSUE 2”)
The Examiner finds that the scope of the claimed “translation” is
limited to the embodiments in the ’274 patent that are said to require using
implied translation logic equations that vary based on whether (1) a density
transition bit is a row, column, or internal bank address bit, or (2) the
implementation multiplies memory devices per rank or multiplies the
number of ranks per memory module. RAN 10 (citing the ’274 patent, col.
22, ll. 15-27). Based on this construction, the Examiner finds that QBMA’s
(1) switching from “C” to “A or B” on page 17, and (2) converting signals

the statement of this proposed rejection which is consistent with the request.
RAN 9. Accord Request, at 95-96.
8 For clarity, we refer to the issue numbers corresponding to those used by
the parties and the Examiner.
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via a 2:4 decoder on page 24 does not teach or suggest the recited
translation, nor does JEDEC cure that deficiency. RAN 10. Based on these
perceived shortcomings of QBMA and JEDEC, the Examiner did not adopt
the proposed obviousness rejection over these references. RAN 9-10.
Requester argues that the Examiner’s construction of “translate” is
unreasonably narrow when interpreted in light of the Specification. App. Br.
13-19. According to Requester, the ’274 patent expressly states that the
term “translate” means to transition from a first set of address and command
signals compatible with one memory density to a second set of address and
command signals compatible with another memory density. App. Br. 15;
Reb. Br. 1 (citing the ’274 patent, col. 32, l. 66 – col. 33, l. 10). As such,
Requester contends, properly construing “translate” in the independent
claims must at least include translating address signals, particularly because
this functionality is separately recited in various dependent claims. App. Br.
17-19; Reb. Br. 2. According to Requester, QBMA’s replacing a system
address bit with a timing signal constitutes address translation between
system and physical memory domains under the broadest reasonable
interpretation of the term “translate.” App. Br. 32; Reb. Br. 8.
Patent Owner argues that the Examiner correctly concluded that
“translation,” as construed, does not encompass the cited portions of QBMA,
because every embodiment directed to translation in the ’274 patent is said
to use translation logic equations to translate from the system memory
domain to the physical memory domain. Resp. Br. 6-8. According to Patent
Owner, QBMA does not disclose the recited translation because there is no
change in the address and control lines sent from the computer system to the
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memory devices as shown on page 24. Resp. Br. 7-8. Patent Owner adds
that QBMA does not disclose the recited translation even under Requester’s
interpretation because QBMA’s switch on page 18 merely connects system
data lines C[0,7] to those of both ranks A[0,7] and B[0,7] for the entire write
cycle, but does not alternate this connection between these ranks, and thus
lacks the interleaved address bit according to Requester’s address translation
position. Resp. Br. 9-10.

ISSUE
Under § 103, has the Examiner erred in declining to reject claim 1 by
finding QBMA and JEDEC collectively do not teach or suggest a circuit
configurable to translate between a system memory domain and a physical
memory domain of a memory module as claimed?

ANALYSIS
We begin by construing the key disputed term “translate.” First,
neither party nor the Examiner identifies an express definition of the term
“translate” in the ’274 patent that clearly and unambiguously establishes the
term’s meaning. This absence is notable, for the ’274 patent expressly
defines other recited terms, namely “load,” “isolation,” and “circuit”—albeit
with non-limiting definitions. See ’274 patent, col. 5, ll. 3-13.
Despite the ’274 patent’s not defining “translate” (unlike the other
terms noted above), the Examiner nonetheless construes the term as limited
to the embodiments presented in the ’274 patent disclosure, which requires
the utilization of implied translation logic equations that vary based on
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whether (1) a density transition bit is a row, column, or internal bank address
bit, or (2) the implementation multiplies memory devices per rank or
multiplies the number of ranks per memory module. RAN 10 (citing the
’274 patent, col. 22, ll. 15-27). This relied-upon passage, however, merely
indicates that “[i]n certain embodiments utilizing memory density
multiplication embodiments, . . . [t]he circuit 40 of certain such embodiments
utilizes implied translation logic equations” with the described variations.
’274 patent, col. 22, ll. 15-27 (emphases added).
Confining the interpretation of “translate” to these embodiments is
overly limiting. To be sure, claims are given their broadest reasonable
interpretation in light of the Specification as it would be interpreted by
skilled artisans. Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir.
2005) (en banc) (citations omitted). But this interpretation must not import
limitations from the Specification into the claims. See id. at 1323
(“[A]lthough the specification often describes very specific embodiments of
the invention, we have repeatedly warned against confining the claims to
those embodiments. . . . [C]laims may embrace different subject matter than
is illustrated in the specific embodiments in the specification.”) (citations
and internal quotation marks omitted).
That is precisely the problem with the Examiner’s interpretation.
Although the Examiner’s relied-upon passage from the ’274 patent informs
our interpretation of “translate” in the context of certain memory density
multiplication embodiments that use the described implied logic equations,
we do not limit our construction to those embodiments. To do otherwise
would impermissibly import specific embodiments into the claims.
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We reach this conclusion even assuming, without deciding, that every
embodiment directed to translation in the ’274 patent uses translation logic
equations to translate from the system memory domain to the physical
memory domain as Patent Owner contends. Resp. Br. 6; Tr. 27-28. In this
regard, Patent Owner refers to the ’274 patent’s “Memory Density
Multiplication” section in columns 21 to 30 including the code associated
with Examples 2 and 3 in this section, as well as the discussion associated
with Figures 10A through 11B. Tr. 30. Patent Owner also refers to the
circuit 40 in Figures 9A and 9B that uses, in certain embodiments, logic
(e.g., address or command decoding logic) to translate between a system
memory domain of the computer system and a physical memory domain of
the memory module. Tr. 23; ’274 patent, col. 16, ll. 40-44. Notably, this
translation discussion is not within the ’274 patent’s “Memory Density
Multiplication” section that describes the implied translation logic equations
in column 22, but rather in a separate section entitled “Command Signal
Translation.” See ’274 patent col. 14, l. 38. Nevertheless, Patent Owner
noted at the oral hearing that the translation discussed in column 14 must
incorporate the implied translation logic equations that the Examiner refers
to in column 22. Tr. 23:4-15.
But even assuming, without deciding, that every embodiment directed
to translation in the ’274 patent uses translation logic equations to translate
from the system memory domain to the physical memory domain as Patent
Owner contends (Resp. Br. 6; Tr. 27-28), we still find the Examiner’s
interpretation overly limiting on this record. It is well settled that even if a
patent describes only a single embodiment, the patent’s claims are not
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limited to that embodiment absent a clear intent to limit the claims’ scope
using words or expressions of manifest exclusion or restriction. Liebel-
Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004); see also
Gillette Co. v. Energizer Holdings, Inc., 405 F.3d 1367, 1374 (Fed. Cir.
2005) (“‘[W]ords or expressions of manifest exclusion’ or ‘explicit’
disclaimers in the specification are necessary to disavow claim scope.”).
The Examiner has not identified—nor can we find—any such manifest
exclusionary or restrictive intent on this record to justify the Examiner’s
narrow construction of “translate” as Requester indicates. App. Br. 15. To
the extent that the relied-upon passage in column 22 regarding the implied
translation logic equations is considered to evidence such a manifest
restrictive intent to disavow a broader construction of “translate,” we
disagree.
This is not a case where the Specification defines terms by implication
as Patent Owner contends. Resp. Br. 9. See Phillips v. AWH Corp., 415
F.3d 1303, 1321 (Fed. Cir. 2005) (en banc) (“Even when guidance is not
provided in explicit definitional format, the specification may define claim
terms by implication such that the meaning may be found in or ascertained
by a reading of the patent documents.”) (citations and internal quotation
marks omitted). Rather, this is a case where the recited translation is, at
best, described in connection with certain embodiments: a description that
hardly limits the term’s broadest reasonable interpretation in light of the
Specification.
Accordingly, absent a definition of “translate,” we construe the term with
its plain meaning (i.e., the ordinary and customary meaning given to the term by
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those of ordinary skill in the art). See id. at 1312. The term “translate” is
defined, in pertinent part, as follows: “In computers, to convert from one
format, such as that of data or a file, into another.” Steven M. Kaplan,
WILEY ELECTRICAL & ELECTRONICS ENGINEERING DICTIONARY 800 (2004).
The same dictionary also provides another pertinent definition of “translate”
as “[t]o convert from one format, function, system, or level, to another.” Id.
As noted above, Requester acknowledges that the ’274 patent
expressly states that the term “translate” means to transition from a first set
of address and command signals compatible with one memory density to a
second set of address and command signals compatible with another
memory density. App. Br. 15; Reb. Br. 1 (citing the ’274 patent, col. 32, l.
66 – col. 33, l. 10) (emphases added). We emphasize the term “and” here,
for Requester elsewhere in the Appeal Brief broadens this proposed
construction of the recited translation to translating address and/or control
signals between incompatible memory domains. See App. Br. 16-19. This
broader proposed construction also changes the term “command signals” to
“control signals”—a change that was not specifically disputed and, in any
event, reasonably comports with the nature of the disclosed command
signals. See, e.g.,’274 patent, col. 16, ll. 11-12, 65-66 (listing “refresh” and
“precharge” as exemplary command signals).
Although the ’274 patent repeatedly refers to translating sets of
address and command signals between incompatible memory domains,9 we
nonetheless find that Requester’s broader construction of translating address
and/or control signals between incompatible memory domains is more

9 See, e.g., ’274 patent, col. 15, ll. 16-24; col. 31, ll. 32-39; col. 33, ll. 5-10.
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consistent with the claimed invention, particularly since dependent claim 6 is
limited to translating address signals as Requester indicates. App. Br. 18.
Accord Wang Decl. filed Nov. 28, 2011 (“Wang Decl.”)10 ¶ 10 (noting that
translating signals between system and physical memory domains in the
’274 patent was accomplished by modifying one or more address and
command signals to map one address space to the other). Accord Tr. 10, 13
(confirming Requester’s proposed construction of “translate” as including
translating address or control signals).
Based on the record before us, and given the plain meaning of
“translate” as noted above, we construe the recited translation limitation as
requiring a circuit configurable to convert address and/or control signals
between a system memory domain and a physical memory domain.
With this construction, we find that QBMA does not teach the recited
translation limitation. As shown on pages 17 through 19, QBMA’s switch
(1) connects system data lines C[0,7] to those of both ranks A[0,7] and
B[0,7] in the Write mode, and (2) switches C’s data lines from A to B in the
Read mode. This switching does not constitute the recited memory domain
translation, for there is no persuasive evidence on this record establishing
that this switching converts address and/or control signals between a system
memory domain and a physical memory domain. To the extent that
Requester contends that this switching reassigns a system address bit to
constitute address translation (see App. Br. 13; Reb. Br. 8 (citing Wang

10 The Wang Declaration is provided in the Evidence Appendix of
Requester’s Rebuttal Brief. Reb. Br. 11.
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Decl. ¶ 13)), we find such an argument unavailing for the reasons indicated
by Patent Owner. Resp. Br. 10.
Nor are we persuaded that QBMA’s exemplary controller on page 24
teaches the recited memory domain translation. As Patent Owner indicates,
the legend adjacent the uppermost arrow on QBMA’s page 24 shows that
there is no change in the address and control lines between the computer
system and memory devices. Resp. Br. 7 (citing Sechen Decl. ¶¶ 11, 16).
This lack of change tends to suggest that there is no associated translation,
namely an address and/or control signal conversion, between the system
memory and physical memory domains.
To be sure, QBMA’s controller on page 24 includes a 2:4 decoder
with (1) two unlabeled inputs directed from the controller, and (2) four “FET
ENABLE DIMM” outputs provided to the memory device connectors.
Notably, the Examiner indicates that this decoder appears to show that
signals are converted between a computer system controller and a memory
module physical memory domain. RAN 10. But even if we were to accept
the Examiner’s position in this regard, QBMA’s decoder is nevertheless not
used for memory locating addressing, but rather for an entirely different
purpose, namely controlling FET switches to reduce capacitive loading as
Dr. Sechen indicates. Sechen Decl. ¶¶ 17, 20. Rather, the signals associated
with QBMA’s address and control lines are the signals pertinent to the
recited memory domain translation limitation under our construction. See
Sechen Decl. ¶¶ 17-22. Accord Tr. 36 (noting this fact). Because these
signals do not change as noted above, there is no translation as claimed.
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Therefore, we are not persuaded that the Examiner erred by not
rejecting independent claim 1 over QBMA and JEDEC. We reach a similar
conclusion regarding (1) independent claims 28, 39, 56, 65, 66, 74, 84, and
96 which recite commensurate translation limitations, and (2) dependent
claims 4-17, 23, 29, 30, 32-34, 40, 41, 44-47, 54, 55, 57-61, 63, 64, 69, 75,
76, 79, 85, 86, 88, 89, 94, and 95 not separately argued with particularity.

THE PROPOSED REJECTION OVER QBMA AND DELL (“ISSUE 3”)
Regarding claim 1, the Examiner finds that although Dell teaches
address translation (remapping) circuitry that would have been compatible
with QBMA’s system, the combination does not teach or suggest the type of
translation claimed, namely requiring the embodiments in the ’274 patent
with the implied translation logic equations noted above. RAN 11, 22-25.
Requester argues that the Examiner’s construction of “translate” is too
narrow because the claim does not preclude Dell’s address translation
(remapping) that translates between incompatible memory domains using
“excess-bit translation.” App. Br. 19-21; Reb. Br. 4-5. Requester adds that
QBMA also translates between incompatible memory domains. App. Br.
22-24.
Patent Owner contends that Dell’s remapping an address bit to a bank
address bit does not translate between memory domains as claimed. Resp.
Br. 11. Patent Owner adds that not only would skilled artisans not have
combined the QBMA and Dell as proposed, Dell does not teach or suggest a
different memory density per rank between the system and physical memory
domains as claimed. Resp. Br. 13.
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ISSUE
Under § 103, has the Examiner erred in declining to reject claim 1 by
finding QBMA and Dell collectively do not teach or suggest a circuit
configurable to translate between a system memory domain and a physical
memory domain of a memory module, where the physical memory domain
has a memory density per rank less than that of the system memory domain?

ANALYSIS
We begin by noting that the Examiner’s decision to not adopt the
proposed rejection over QBMA and Dell is based solely on the Examiner’s
finding that these references do not teach or suggest the recited translation
that is said to require the implied translation logic equations described in
column 22 of the ’274 patent as noted above. RAN 11, 22-25. Notably, in
addressing Patent Owner’s arguments regarding the physical memory
domain having a memory density per rank less than that of the system
memory domain, the Examiner apparently finds these arguments
unpersuasive in connection with Issues 3 and 7 as not commensurate with
the scope of the associated memory density limitation in claim 1, but
nonetheless deems these arguments moot in view of the Examiner’s narrow
construction of the translation limitation. RAN 22-25.11 Accord Reb. Br. 8-
9 (noting this position).

11 See also RAN 20-21 (agreeing with the Wang Declaration’s interpretation
of “rank”); RAN 22 (construing “memory density per rank”).
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The Examiner also finds that Dell’s address translation (remapping)
circuitry “would have been compatible with” QBMA’s system, thus
indicating the references’ combinability and suggesting that the Examiner
was unpersuaded by Patent Owner’s contrary arguments in this regard.
RAN 11.12 Despite this indicated combinability of QBMA and Dell, the
Examiner’s narrow construction of the recited translation limitation was
nonetheless dispositive in the Examiner’s decision to not reject the claims
over these references. See id.
But as noted above, the Examiner’s construction of the recited
translation limitation is too narrow because this limitation is not limited to
the embodiments that use the implied translation logic equations described
in the ’274 patent’s column 22. Rather, under its broadest reasonable
interpretation, the translation limitation requires a circuit configurable to
convert address and/or control signals between a system memory domain
and a physical memory domain.
Turning to the prior art, Dell’s logic circuit (application specific
integrated circuit (ASIC)) 24 effects an address remapping function 50 such
that a four-bank memory device 22 can be used with system 12 that expects
or requires a two-bank memory device. Dell, col. 4, ll. 24-58; Fig. 1. To
this end, the remapping function 50 connects the highest order address signal
(“A12” in Figure 1A) to the “BA1” input pin of the memory devices 22.
Dell, col. 8, ll. 11-58.

12 Accord Wang Decl. ¶ 12 (explaining why “[a] person who was practicing
in the field of memory devices, modules and systems at the time the ‘652
patent application was filed would have been motivated to combine QBMA
and Dell.”)
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We agree with the Examiner that Dell’s remapping circuit translates
addresses. RAN 11. And we agree with Requester (App. Br. 19-21) that
nothing in claim 1 precludes Dell’s address translation circuit, for it converts
at least address signals between a system memory domain and a physical
memory domain. Even assuming, without deciding, that the total number of
address signals (14) remains the same after Dell’s conversion as Patent
Owner contends (Resp. Br. 11-12), nothing in claim 1 precludes the address
translation that occurs resulting from this conversion, even if it is limited to
the system’s internal organization.
Given Dell’s teachings in combination with QBMA and the
Examiner’s findings that these references are combinable as noted above, the
weight of the evidence on this record favors Requester’s position.
Therefore, we are persuaded that the Examiner erred in not rejecting
independent claim 1 over QBMA and Dell. We reach a similar conclusion
regarding (1) independent claims 28, 39, 56, and 84 which recite
commensurate limitations, and (2) dependent claims 2, 3, 18-22, 24-27, 31,
35-38, 42, 43, 48-53, 62, 67, 68, 70-73, and 87 for similar reasons.

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THE PROPOSED REJECTION OVER WONG AND KARABATSOS
(“ISSUE 6”)

Regarding independent claim 1, the Examiner finds that Wong’s
address decoding system does not require the recited type of translation in
the embodiments of the ’274 patent that use the implied translation logic
equations noted above. RAN 13-14, 24-25.
Requester argues that Wong translates between incompatible memory
domains using “excess-bit translation” by using the highest order address bit
to translate from a first set to a second set of address signals, each set
compatible with different respective memory domains. App. Br. 26-27;
Reb. Br. 6.
Patent Owner contends that Requester’s reliance on Wong’s address
bit “A13” as a “transition bit” to translate by selecting between upper and
lower memory banks is flawed given various teachings of Wong, including
the values in the table of Wong’s Figure 6. Resp. Br. 16-18. Patent Owner
adds that Wong’s asynchronous memory system cannot be used with
synchronous memory systems with DDR memory devices. Resp. Br. 18.

ISSUE
Under § 103, has the Examiner erred in declining to reject claim 1 by
finding Wong and Karabatsos collectively do not teach or suggest a circuit
configurable to translate between a system memory domain and a physical
memory domain of a memory module?

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ANALYSIS
We begin by noting, as does the Examiner,13 that the proposed
rejection pertaining to Issue 6 relies on Wong—not Karabatsos—for
teaching the recited translation limitation. Accord Request, at 249-50. As
Patent Owner indicates, while Karabatsos may have been relied upon for
translation in connection with other issues during reexamination (e.g., Issues
4 and 5), the proposed grounds of rejection articulated in connection with
those issues were not appealed and are, therefore, not before us. Resp. Br.
13. Accordingly, despite Requester’s arguments to the contrary (Reb. Br. 7),
we need not address Requester’s arguments in connection with Karabatsos’
teaching the recited translation limitation. App. Br. 28. In any event,
because the relied-upon aspects of Karabatsos in connection with Issue 6 are
undisputed, we confine our discussion to Wong.
Turning to Wong, the disclosed memory expansion module includes
multiple memory banks 1022, 1012 connected to a bank control circuit 2000
that uses an address signal “A13” as a bank selection input. Wong, Abstract;
col. 4, ll. 13-42; Fig. 3. The selected memory bank depends on the logic
level of the address input to the bank control circuit. Wong, col. 2, ll. 49-53.
Notably, it is undisputed that Wong decodes addresses, at least those in
connection with address signal “A13” (i.e., the most significant address bit).
See RAN 14 (characterizing the functionality of Wong’s column four as

13 See RAN 14 (“[T]he request does not show that Wong or Karabatsos,
either alone or in combination, explicitly teaches translation or mapping, as
described in the request. Karabatsos has not been cited to teach this
feature.”) (emphasis added).
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decoding addresses); see also Resp. Br. 18 (referring to Wong’s decoding
the “A13” bit).
The Examiner, however, finds that Wong’s address decoding does not
require the recited translation that is limited to the embodiments that require
the implied translation logic equations described in column 22 of the ’274
patent as noted above. RAN 14. But as noted previously, the Examiner’s
construction of the recited translation limitation is too narrow because this
limitation is not limited to these embodiments under its broadest reasonable
interpretation. Rather, the translation limitation requires a circuit
configurable to convert address and/or control signals between a system
memory domain and a physical memory domain.
We see no reason why Wong’s acknowledged address decoding
functionality does not meet that conversion requirement. A “decoder” is
defined in pertinent part as “[a] device or program routine that converts
coded data back to its original form. This can mean changing unreadable or
encrypted codes into readable text or changing one code to another,
although the latter type of decoding is usually referred to as conversion.”
MICROSOFT COMPUTER DICTIONARY 149 (5th ed. 2002) (emphases added).
The same dictionary alternatively defines “decoder” as follows: “In
electronics or hardware, a type of circuit that produces one or more selected
output signals based on the combination of input signals it receives.” Id.
Under either definition, Wong’s acknowledged address decoding
functionality at least involves converting address data—a conversion of
address signals that reasonably comports with the translation limitation
under its broadest reasonable interpretation.
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Even assuming, without deciding, that Wong’s “A13” bit is not a
“transition bit” as Patent Owner contends (Resp. Br. 16-17), it is nonetheless
undisputed that Wong decodes addresses, at least regarding those associated
with address signal “A13” (i.e., the most significant address bit).
Accordingly, Patent Owner’s arguments are not commensurate with the
scope of the recited translation limitation that does not preclude this address
decoding functionality.
Accordingly, the weight of the evidence on this record favors
Requester’s position. Therefore, we are persuaded that the Examiner erred
in not rejecting independent claim 1 over Wong and Karabatsos. We reach a
similar conclusion regarding (1) independent claims 28, 39, 56, and 84
which recite commensurate limitations, and (2) dependent claims 2-14, 16-
21, 23-27, 29-38, 40-48, 50-53, 55, 57-64, 66-83, 85-94, 96, and 97 for
similar reasons.

THE PROPOSED REJECTION OVER DELL AND KARABATSOS
(“ISSUE 7”)

We are also persuaded that the Examiner erred in declining to reject
claims 1-6, 8-14, 16, 18-46, 48-64, and 67-97 over Dell and Karabatsos for
the reasons indicated previously. In an analysis similar to Issue 3, the
Examiner finds that while Dell teaches address translation (remapping)
circuitry that would have been compatible with Karabatsos’ system, the
combination does not teach or suggest the type of translation claimed,
namely requiring the embodiments with the implied translation logic
equations noted above. RAN 15, 20-25. But as noted above, we agree with
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Requester (App. Br. 30-31; Reb. Br. 7) that the Examiner’s construction is
too limiting, and that the Examiner erred by not rejecting the claims based
on Dell’s acknowledged address translation functionality.
Patent Owner contends that the Examiner found that Dell and
Karabatsos fail to disclose translation between system and physical memory
domains with different densities per rank or device, and that this purported
deficiency was an independent reason for confirming or allowing the claims.
Resp. Br. 19. The record, however, does not support this contention.
Notably, in addressing Patent Owner’s arguments regarding the physical
memory domain having a memory density per rank less than that of the
system memory domain, the Examiner apparently finds these arguments
unpersuasive in connection with Issues 3 and 7 as not commensurate with
the scope of the associated memory density limitation in claim 1, but
nonetheless deems these arguments moot in view of the Examiner’s narrow
construction of the translation limitation. RAN 22-25.14 Accord Reb. Br. 8-
9 (noting this position).
In short, the Examiner’s narrow construction of the translation
limitation—not the memory density per rank limitation—was dispositive in
the Examiner’s decision to not reject claims 1-6, 8-14, 16, 18-46, 48-64, and
67-97 over Dell and Karabatsos. But as noted above, this decision was
erroneous.

14 See also RAN 20-21 (agreeing with the Wang Declaration’s interpretation
of “rank”); RAN 22 (construing “memory density per rank”).
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THE REMAINING APPEALED PROPOSED REJECTIONS
(“ISSUES 8-12”)

In view of the Examiner’s overly-narrow construction of the
translation limitation noted above in connection with independent claims 1,
28, 39, 56, 74, 84, and 96, the Examiner also erred in not rejecting the
remaining appealed proposed rejections of dependent claims 98-104 as
follows:

Dell and Karabatsos
(“Issue 7”)
QBMA and Dell
(“Issue 8”)
Karabatsos and Dell
(“Issue 9”)
QBMA, Dell, and Kazuo
(“Issue 10”)
Karabatsos, Dell, and Kazuo
(“Issue 11”)
Wong, Karabatsos, and Kazuo
(“Issue 12”)

RAN 15-19.
Despite nominally arguing these proposed grounds of rejection
separately, the parties reiterate previous arguments regarding the translation
limitation. App. Br. 24-25, 30-31; Resp. Br. 19; Reb. Br. 7-8. Because the
Examiner erred in not rejecting independent claims 1, 28, 39, 56, 74, 84, and
96 based on the Examiner’s overly narrow construction of the translation
limitation, we also find that the Examiner erred by not rejecting dependent
claims 98-104 for similar reasons.

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CONCLUSION
Under § 103, the Examiner did not err in declining to reject claims 1,
4-17, 23, 28-30, 32-34, 39-41, 44-47, 54-61, 63-66, 69, 74-76, 79, 84-86, 88,
89, and 94-96 over QBMA and JEDEC. Accordingly, we affirm that
decision.
Under § 103, the Examiner erred in declining to reject (1) claims 1-3,
18-22, 24-28, 31, 35-39, 42, 43, 48-53, 56, 62, 67, 68, 70-73, 84, and 87
over QBMA and Dell; (2) claims 1-14, 16-21, 23-48, 50-53, 55-64, 66-94,
96, and 97 over Wong and Karabatsos; (3) claims 1-6, 8-14, 16, 18-46, 48-
64, 67-97 over Dell and Karabatsos; (4) claims 98-104 over QBMA and
Dell; (5) claims 98-104 over Karabatsos and Dell; (6) claims 98-104 over
QBMA, Dell, and Kazuo; (7) claims 98-104 over Karabatsos, Dell, and
Kazuo; and (8) claims 98-104 over Wong, Karabatsos, and Kazuo.
Accordingly, we reverse that decision.

ORDER
The Examiner’s decision declining to reject claims 1-104 is affirmed-
in-part.
Under 37 C.F.R. § 41.77(a), the above-noted reversal constitutes a
new ground of rejection. Section 41.77(b) provides that “a new ground of
rejection . . . shall not be considered final for judicial review.” That section
also provides that Patent Owner, WITHIN ONE MONTH FROM THE
DATE OF THE DECISION, must exercise one of the following two options
with respect to the new grounds of rejection to avoid termination of the
appeal proceeding as to the rejected claims:
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(1) Reopen prosecution. The owner may file a response
requesting reopening of prosecution before the examiner. Such
a response must be either an amendment of the claims so
rejected or new evidence relating to the claims so rejected, or
both.

(2) Request rehearing. The owner may request that the
proceeding be reheard under § 41.79 by the Board upon the
same record. The request for rehearing must address any new
ground of rejection and state with particularity the points
believed to have been misapprehended or overlooked in
entering the new ground of rejection and also state all other
grounds upon which rehearing is sought.

In accordance with 37 C.F.R. § 41.79(a)(1), the “[p]arties to the
appeal may file a request for rehearing of the decision within one month of
the date of . . . [t]he original decision of the Board under § 41.77(a).” A
request for rehearing must be in compliance with 37 C.F.R. § 41.79(b).
Comments in opposition to the request and additional requests for rehearing
must be in accordance with 37 C.F.R. § 41.79(c)-(d), respectively. Under 37
C.F.R. § 41.79(e), the time periods for requesting rehearing under paragraph
(a) of this section, for requesting further rehearing under paragraph (c) of
this section, and for submitting comments under paragraph (b) of this section
may not be extended.
An appeal to the United States Court of Appeals for the Federal
Circuit under 35 U.S.C. §§ 141-44 and 315 and 37 C.F.R. § 1.983 for an
inter partes reexamination proceeding “commenced” on or after November
2, 2002 may not be taken “until all parties’ rights to request rehearing have
been exhausted, at which time the decision of the Board is final and
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appealable by any party to the appeal to the Board.” 37 C.F.R. § 41.81. See
also MPEP § 2682 (8th ed., Rev. 8, July 2010).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED-IN-PART
37 C.F.R. § 41.77

alw

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Patent Owner:

The Law Office of Jamie Zheng, Ph.D. Esq.
P.O. Box 60573
Palo Alto, CA 94306

Third Party Requester:

Pillsbury, Winthrop, Shaw, Pittman LLP
2475 Hanover Street
Palo Alto, CA 94304-1114