Ex Parte 7080301 et al

Patent Trial and Appeal Board

Feb 26, 2014

95001579 (P.T.A.B. Feb. 26, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,579 03/18/2011 7080301 3059.704REX3 5475
26111 7590 02/26/2014
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
SORRELL, ERON J
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
02/26/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
______________

XILINX, INC.,
Third-Party Requester, Appellant, and Respondent

v.

INTELLECTUAL VENTURES MANAGEMENT, OF WHICH
INTELLECTUAL VENTURES I LLC IS AN AFFILIATE,
Patent Owner, Appellant, and Respondent
______________

Appeal 2014-001224
Reexamination Control No. 95/001,579
United States Patent 7,080,301 B2
1

Technology Center 3900
______________

Before JOHN C. MARTIN, JOHN A. JEFFERY, and
JENNIFER L. MCKEOWN, Administrative Patent Judges.

MARTIN, Administrative Patent Judge.

1
Issued July 18, 2006, based on Application 11/261,762, filed October 31,
2005, which is identified as a continuation of Application No. 10/767,265,
filed January 30, 2004 (now Patent 6,964,001), which is identified as a
continuation of Application 09/275,726, filed March 24, 1999 (now
Patent 6,687,865) (hereinafter “grandparent ’865 patent”). The Certificate
of Correction dated February 1, 2011, in Patent 7,080,301 B2 (hereinafter
the ’301 patent”) made no changes relevant to the merits of the appeals
before us.
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DECISION ON APPEAL
Intellectual Ventures Management (hereinafter “Patent Owner”)
appeals the Examiner’s rejection of original claims 1-6 of and proposed new
claims 7-26 for the ’301 patent on various grounds. Xilinx, Inc., (hereinafter
“Requester”) appeals the Examiner’s refusal to additionally reject these
claims on other grounds. We have jurisdiction under 35 U.S.C. §§ 6, 134,
and 315.
We AFFIRM all of the Examiner’s rejections and AFFIRM the
Examiner’s decision not to enter Requester’s additional proposed rejections.

I. STATEMENT OF THE CASE
A. Related Litigation
The ’301 patent is described as “the subject of declaratory judgment
claims of non-infringement and invalidity in Xilinx, Inc. v. Invention
Investment Fund I LP et al., Case No. 5:11-cv-00671-EJD (N. D. Cal.).”
PATENT OWNER’S APPEAL BRIEF TO THE PATENT TRIAL AND
APPEAL BOARD, filed March 8, 2013 (hereinafter “P.O. Appeal Br.”) 4,
para. II.c. On February 7, 2013, the court dismissed these claims pursuant to
a stipulation filed by the parties. Id.

B. This Inter Partes Reexamination Proceeding
The REQUEST FOR INTER PARTES REEXAMINATION
(hereinafter “Request”), which was filed on March 18, 2011, proposes
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rejections #1-#4 of original patent claims 1-6 under 35 U.S.C. §§ 102 and
103 based on either of Zorian
2
and Franklin.
3
These proposed rejections are
described in claim charts submitted as Exhibits AA and BB to the Request.
In response to an Amendment adding claims 7-26,
4
Requester filed
comments including proposed rejections #5 to #12 of the new claims,
additionally relying on Sauerwein
5
with respect to some claims.
6
These
proposed rejections are described in claim charts identified as Exhibits CC-
HH.
A Right of Appeal Notice (RAN) was mailed on December 12, 2012.
The Examiner’s Answer, which incorporates the RAN by reference without
providing any further analysis, was mailed on July 12, 2013.
In addition to Patent Owner’s Appeal Brief, the following briefs are
before us:

2
Yervant Zorian, Test Requirements for Embedded Core-based Systems and
IEEE P1500, International Test Conference 1997 (Nov. 1-6, 1997). Request
Ex. C.
3
Manoj Franklin & Kewal K. Saluja, Built-in Self-Testing of Random-
Access Memories, COMPUTER (Oct. 1990). Request Ex. D.
4
REPLY TO OFFICE ACTION IN INTER PARTES REEXAMINATION,
filed July 5, 2011, at 5-7.
5
Sauerwein, et al., U.S. 5,526,286, issued June 11, 1996.
6
COMMENTS BY THIRD PARTY REQUESTER PURSUANT TO
37 CFR § 1.947, filed August 4, 2011, at 23-24 paras. 5-12.
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(1) THIRD PARTY REQUESTER’S APPEAL BRIEF IN INTER
PARTES REXAMINATION PURSUANT TO 37 C.F.R. § 41.67, filed
March 8, 2013 (hereinafter “Req. Appeal Br.”);
(2) “Patent Owner’s Respondent Brief,” filed April 8, 2013
(“P.O. Resp’t Br.”);
(3) THIRD PARTY REQUESTER’S RESPONDENT BRIEF IN
INTER PARTES REXAMINATION PURSUANT TO 37 C.F.R. § 41.68,
filed April 10, 2013 (“Req. Resp’t Br.”); and
(4) PATENT OWNER’S REBUTTAL BRIEF PURSUANT TO
37 C.F.R. § 41.71, filed August 12, 2013 (“P.O. Reb. Br.”).

C. The Principal Issue Before Us
The principal issue before us is how to interpret “normal system
operation” in the phrase “capture and analysis of system operation signals
during normal system operation” in the “wherein” clauses of independent
claims 1 and 4.

D. The Invention Described in the ’301 Patent
The invention described in the ’301 patent relates to on-chip circuits
for the test and diagnosis of problems in integrated circuits. ’301 patent
1:21-24. In accordance with the invention, special on-chip circuits are used
to observe the internal workings of an integrated circuit (IC). Id. at 2:42-44.
These circuits operate at internal IC clock rates so that the limitations of the
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frequency of signals at the IC input and output (I/O) boundary are avoided.
Id. at 2:44-47. Many more points in the IC system are accessed than is
feasible with conventional external test and debug processors. Id. at 2:47-
49.
Figure 1a of the ’301 patent is reproduced below.

Figure 1a is a diagram of an exemplary IC 100 having a host processor
connected by a system bus and a peripheral bus to various circuit blocks,
including, for example, a third-party core and a user-developed core. Id. at
6:14-21.

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Figure 1b is reproduced below.

Figure 1b is a diagram of an IC 100 in accordance with the invention, which
includes a Service Processor Unit (SPU) 101 coupled to an IC system bus
105 and to an added test bus 104. Id. at 6:22-26. Test wrappers 102, which
are formed by the serial connection of block I/O connector circuits 310
(Fig. 4a), discussed infra, are connected to test bus 104 to provide test
communication channels into selected blocks 106. Id. at 6:26-28; 7:33-36.
7

7
Figures 4a and 4b are reproduced and considered infra in the discussion of
how to interpret the claim phrase “normal system operation.”
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SPU 101 provides a connection for an external diagnostics console 103 to
view and test the internal workings of IC 100. Id. at 6:29-31.
Figure 2 is reproduced below.

Figure 2 illustrates one embodiment of the architecture of SPU 101. Id. at
3:54-55. SPU 101 has a number of extended function units (EFUs),
including a control unit (e.g., microprocessor 211), a buffer memory unit
218, an analysis engine 215, a scan control unit 222, an interrupt handler 221
(further connected to a range check unit 220), a system bus interface 214, a
test bus interface 213, and a built-in self test (BIST) engine 212. Id. at
6:32-38.
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In one embodiment of the invention, an EFU carries out the functions
of a logic analyzer that captures and stores signal state values in a digital
system following the occurrence of a pre-defined event. Id. at 5:4-7. Two
different types of logic probes may be used with the logic analyzer EFU. Id.
at 5:31-32. One type of logic probe, termed a “digital probe,” captures
sequences of digital signals from internal points of the IC. Id. at 5:32-34.
These digital signals are also referred to as “probe signals” (id. at 8:42-43)
and as “system operation signals.” See id. at 3:7-10 (“The integrated circuit
also has a plurality of probe lines which are responsive to the control unit for
carrying system operation signals at predetermined probe points of the logic
blocks.”). The phrase “system operation signals” also appears in claims 1
and 4.
The second type of logic probe is an analog probe, which captures
signal events representing the detection of signal integrity conditions, such
as ground bounce. Id. at 5:60-63. The range check unit 220 is connected to
analog probe lines 201 and processes their values to detect any out-of-range
conditions, which are signaled to interrupt handler 221. Id. at 6:49-52.
Trigger logic that is responsive to a predetermined trigger event can be used
to stop the data capture operations. Id. at 14:28-31.
8
Alternatively, a trigger
event can be used to start the data capture operations. Id. at 11:62-65.

8
Figures 9c and 9d show such trigger logic. ’301 patent 11:16-60.
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Figure 2 shows a single “core block” 106 having a corresponding test
wrapper 102 that is connected to test bus 104. Core block 106 also includes
a scan string 403 that is connected to test bus 104. Id. at 6:62-64. Scan
string 403 is formed by serially connecting block scan connector circuits 320
(Fig. 4b) (id. at 8:28-29), discussed infra.
Figure 3a is reproduced below.

Figure 3a is a diagram that illustrates the coupling between test wrappers,
scan strings, probe strings and range probes to a test bus. Id. at 3:56-57.
“Through test bus connector[s] 401, the test bus 104 is selectively connected
to test wrappers 102, scan string lines 403, probe string lines 402 and trigger
lines 204.” Id. at 7:3-5. A probe string 402 is formed by “serially
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connecting the probe-in terminal of a connector circuit 310 [Fig. 4a] and 320
[Fig. 4b] to the probe-out terminal of another connector circuit 310 and
320.” Id. at 9:4-6.
Figure 3c is reproduced below.

Figure 3c shows an embodiment of coupling a trigger line 204, probe
string 402, test wrapper 102, and scan string line 403 to three lines of test
bus 104. Id. at 7:27-29.

E. The Claims
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The only independent claims on appeal are original patent claims 1
and 4, which are reproduced below. The disputed phrase “normal system
operation” appears in the “wherein” clause of each claim.
1. An integrated circuit comprising:
one or more logic blocks generating one or more system
operation signals at one or more system operation clock rates;
and
a service processor unit to perform test and debug
operations of said logic blocks of said integrated circuit, further
comprising:
a control unit;
a buffer memory;
an analysis engine;
a scan control unit,
a test bus interface; and
a built-in self test (BIST) engine;
wherein, in a first mode of operation, said service
processor unit performs capture and analysis of system
operation signals during normal system operation through said
test bus interface.

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4. An integrated circuit comprising:
one or more logic blocks generating one or more system
operation signals at one or more system operation clock rates;
and,
a service processor unit to perform test and debug
operations of at least one of said logic blocks of said integrated
circuit, further comprising:
a control unit;
a buffer memory;
an analysis engine; and
a system bus interface;
wherein, in a first mode of operation, said service
processor unit performs capture and analysis of system
operation signals during normal system operation through said
system bus interface.
Claims App. (Req. Appeal Br. 28).

F. The Rejections Challenged by Patent Owner
Patent Owner (P.O. Appeal Br. 6) challenges the following rejections
entered by the Examiner:
1. Claims 1-10 and 12-26 under 35 U.S.C. § 102(a) for anticipation by
Zorian. RAN 9, 32.
2. Claims 1-6, 9, 10, 12-16, and 20-25 under 35 U.S.C. § 102(b) for
anticipation by Franklin. Id. at 22, 43.
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3. Claims 7, 8, and 17-19 under 35 U.S.C. § 103(a) for obviousness
over Franklin in view of Zorian. Id. at 51.
4. Claim 11 under § 103(a) for obviousness over Zorian in view of
Sauerwein. Id. at 56.
5. Claim 11 also under 35 U.S.C. § 103(a) for obviousness over
Franklin in view of Sauerwein. Id. at 57.
9

G. The Unadopted Proposed Rejections That Are the Subject of
Requester’s Appeal
Requester (Req. Appeal Br. 5-6, sec. VI) challenges the Examiner’s
refusal to adopt the following proposed rejections under 35 U.S.C. § 103(a):
1. Claims 1-10 and 12-26 based on Zorian (Proposed Rejections #2
and #6) (identified by Requester as corresponding to “RAN Ground 2” and
“RAN Ground 6”). RAN 58.
2. Claims 1-6, 9, 10, 12-16, and 20-25 based on Franklin (Proposed
Rejections #4 and #10). Id. at 58-59.
3. Claims 9, 10, 14-16, 20, 23, and 25 based on Zorian in view of
Sauerwein (Proposed Rejection #7). Id. at 56.
4. Claims 12 and 21 based on Zorian in view of Franklin (Proposed
Rejection #8). Id. at 59.

9
Patent Owner’s Appeal Brief incorrectly states at page 6 that this ground
of rejection applies to claims 9-11, 14-16, 20, 23, and 25 but correctly
identifies it at page 23 as limited to claim 11.
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5. Claims 9, 10, 14-16, 20, 23, and 25 based on Franklin in view of
Sauerwein (Proposed Rejection #11). Id. at 57.

H. Patent Owner’s Declaration Evidence
10

Patent Owner relies on the following expert declarations by Dr. Ajay
Khoche:
1. DECLARATION OF AJAY KHOCHE, B.ENGR., M.TECH.,
PH.D. UNDER 37 C.F.R. § 1.132, dated July 5, 2011 (hereinafter cited as
“Khoche I”). P.O. Appeal Br. Evid. App.
2. SECOND DECLARATION OF AJAY KHOCHE, PH.D. UNDER
37 C.F.R. § 1.132, dated August 22, 2012 (“Khoche II”). Id.

I. Requester’s Declaration Evidence
11

Requester relies on the following expert declarations by Dr. M. Ray
Mercer:
1. “Declaration Under 37 C.F.R. § 1.132 [o]f M. Ray Mercer, Ph.D.,”
dated August 4, 2011 (“Mercer I”). Req. Appeal Br. Ex. 7.
2. “Second Declaration Under 37 C.F.R. § 1.132 of M. Ray Mercer,
Ph.D.,” dated September 20, 2012 (“Mercer II”), which addresses statements
made in the Second Khoche Declaration. Req. Appeal Br. Ex. 9.

10
Discussed at RAN 65-68.
11
Discussed at RAN 68.
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II. CLAIM INTERPRETATION
A. Claim Interpretation During Reexamination
“During reexamination, as with original examination, the PTO must
give claims their broadest reasonable construction consistent with the
specification.” In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379
(Fed. Cir. 2007) (citing In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359,
1364 (Fed. Cir. 2004)). “[T]he ordinary and customary meaning of a claim
term is the meaning that the term would have to a person of ordinary skill in
the art in question at the time of the invention, i.e., as of the effective filing
date of the patent application.” Phillips v. AWH Corp., 415 F.3d 1303, 1313
(Fed. Cir. 2005) (en banc). It is improper, when in giving claims their
broadest reasonable interpretation, to read limitations from the specification
into the claims:
[A]lthough the specification often describes very specific
embodiments of the invention, we have repeatedly warned
against confining the claims to those embodiments. . . . In
particular, we have expressly rejected the contention that if a
patent describes only a single embodiment, the claims of the
patent must be construed as being limited to that embodiment.
Phillips, 415 F.3d at 1323 (citations omitted).
The expert testimony before us has been considered in accordance
with the following principles:
[E]xtrinsic evidence in the form of expert testimony can be
useful to a court for a variety of purposes, such as to provide
background on the technology at issue, to explain how an
invention works, to ensure that the court’s understanding of the
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technical aspects of the patent is consistent with that of a person
of skill in the art, or to establish that a particular term in the
patent or the prior art has a particular meaning in the pertinent
field. . . . However, conclusory, unsupported assertions by
experts as to the definition of a claim term are not useful to a
court. Similarly, a court should discount any expert testimony
“that is clearly at odds with the claim construction mandated by
the claims themselves, the written description, and the
prosecution history, in other words, with the written record of
the patent.”
Phillips, 415 F.3d at 1318.

B. The Meaning of “Normal System Operation” (Claims 1 and 4)
As an initial matter, we note it appears to be undisputed that the “first
mode of operation” recited in claims 1 and 4 and “second mode of
operation” recited in dependent claims 2 and 5 refer to operation of the
recited “service processor unit.”
Claims 1 and 4, which are apparatus claims, do not recite or require
the actual performance of “normal system operation” of the integrated
circuit. Instead, these claims require that the integrated circuit be capable of
“normal system operations” during which the recited “service processor
unit” can perform “capture and analysis of system operation signals . . .
through said . . . bus interface.” See In re Hallman, 65 F.2d 212, 215 (CCPA
1981) (“To the extent that the process limitations distinguish the products
over the prior art, they must be given the same consideration as traditional
product characteristics.”) (citation omitted).
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The phrase “normal system operation” appears only in claims 1, 4, 9,
and 20 and the Abstract. The similar phrase “normal system operations”
appears in the paragraph at column 14, lines 22-45 (hereinafter “Col. 14,
Lines 22-45”). As explained in more detail below, the ’301 patent describes
block I/O connector circuit 310 (Fig. 4a) as having (1) a “test mode,” during
which its data-in and data-out terminals are used to load test signals into and
retrieve test signal results from a logic block, and (2) a “normal mode,”
during which it performs two functions: (a) providing a” simple path”
between the data-in and data-out terminals and (b) using its probe-in and
probe-out terminals to select probe signals (the claimed “system operation
signals”) for capture and later analysis.
Patent Owner contends that “normal system operation occurs during
normal mode and not during test mode when the IC is performing testing
operations . . . .” P.O. Appeal Br. 14. The Examiner disagrees, concluding
instead that “[t]he term ‘normal system operation’ as used in the Patent
Owner’s claims and specification is not the same as ‘a normal mode of
operation of an integrated circuit (IC)’ in the context of a normal mode and a
test mode” (RAN 62) and that “the term ‘normal system operation’ does not
exclude the IC or portions of the IC from being under test or in a test mode.”
Id. at 63 (emphasis added). Based on this claim interpretation, the Examiner
found that the claim phrase “normal system operation” reads on test modes
described in Zorian and Franklin, each of which describes operation in
normal and test modes.
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Patent Owner’s interpretation of “normal system operations”
(P.O. Appeal Br. 10-13) is based on Dr. Khoche’s declaration testimony and
the following information in the ’301 patent disclosure:
(1) The descriptions of I/O connector circuit 310 (Fig. 4a) and block
scan connector circuit 320 (Fig. 4b);
(2) The description of “normal system operations” in Col. 14,
lines 22-45; and
(3) Dependent claims 2 and 5, which recite a “second mode of
operation” in which the service processor unit “performs tests” on one or
more of the logic blocks.
We begin our analysis with the descriptions of connector circuits 310
and 320, depicted in Figures 4a and 4b. Neither expert witness specifically
discusses these connector circuits.

1. Figures 4a and 4b
Figure 5, which shows the details of a circuit element employed in
each of Figures 4a and 4b, is reproduced below.

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Figure 5 is a diagram showing the details of scan flip flop 301 in Figure 4a
and scan flip flop 311 in Figure 4b. Id. at 8:53-54. This circuit has separate
scan-slave and data-slave sections, thereby allowing a “state signal which
has been scanned into the scan flip-flop . . . to remain unaffected by
functional clock pulses that cause the flip-flop . . . to capture signals on the
data in terminal . . . so that they appear in the data-slave section and on the
data out terminal . . . .” Id. at 8:54-61.

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Figure 4a is reproduced below.

Figure 4a is a circuit diagram of a block input/output connector 310 used in
a test wrapper for observing test points outside a block along a boundary-
scan chain. Id. at 3:61-63. A test wrapper 102 is formed by serially
connecting a plurality of block I/O connector circuits 310. Id. at 7:33-34.
Scan-in terminal 304 of the illustrated connector is connected to scan-out
terminal 306 of an adjacent connector circuit 310 (not shown) in the serial
scan chain of a test wrapper 102. Id. at 7:36-40.
“In the normal operation of the IC, connector circuit 310 provides a
simple path between the block 106 and the rest of the IC 100.” Id. at 7:43-
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45 (emphasis added). This simple path is formed between data-in
terminal 302 and data-out terminal 307, which are connected to a block 106
and the rest of IC 100 in either of two ways, depending on the desired testing
function. If connector circuit 310 is to provide an input signal to the block
106 during test operations, the data-out terminal 307 is connected to the
block 106 and the data-in terminal is connected to the rest of IC 100. Id. at
7:45-49. These connections are reversed if the connector circuit instead is to
receive an output signal from the block 106 during test operations. Id. at
7:49-53. These input signals to and output signals from a block 106
presumably correspond to the “test signals” and “test signal results,”
respectively, in the ’833 patent’s “SUMMARY OF THE INVENTION”:
“The scan lines [formed by scan flip flops 301 of connector circuits 310] are
responsive to the control unit for loading test signals for the logic blocks and
retrieving test signal results from the logic blocks.” Id. at 3:1-4 (emphasis
added). Also, these test signals can take the form of pseudo-random bit
sequences: “Test and debug circuits may contain scan strings that may be . .
. used to provide pseudo-random bit sequences to user-definable logic.” Id.,
Abstract.
A control signal on a “test control line 300” determines whether
connector circuit 310 is operating in “normal mode” or “test mode”:
When the control signal of the line 300 signal is not-asserted,
i.e., normal mode, there is normal operational signal flow
between the data-in terminal 302 and the data-out terminal
307. On the other hand, when the control signal on the line 300
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is in [an] asserted state, i.e., test mode, the current state of the
scan flip-flop 301 is passed onto the data-out terminal 307; the
data-in terminal 302 and the data-out terminal 307 are isolated
from one another.
Id. at 8:8-15 (emphasis added).
Summarizing the above description of connector circuits 310, during
operation of these connector circuits in “test mode” data-in terminal 302 and
data-out terminal 307 are isolated from each another and can be used to
“load[] test signals” into or “retriev[e] test signal results” from a logic block.
Id. at 3:1-4. During operation in “normal mode,” connector circuit 310
provides a “simple path” between data-input and data-output terminals 302
and 307, i.e., “normal operational signal flow between the data-in terminal
302 and the data-out terminal 307.” Id. at 8:8-15.
In addition to performing the operations discussed above, connector
circuits 310 are used to select probe signals (i.e., the claimed “system
operation signals”) for capture and analysis, as recited in the following
language of the “wherein” clauses of claims 1 and 4: “said service processor
unit performs capture and analysis of system operation signals during
normal system operation through said . . . bus interface.” Specifically,
connector circuit 310 has “a probe-in terminal 303 and a probe-out terminal
305 which provide a path for probe signals from selected portions of the
block 106 through the connector circuit 310 to observe operations in the
block 106.” Id. at 7:53-57. This probe signal selection function is
controlled by scan flip-flop 301 of connector circuit 310 as follows:
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The state stored in the scan flip-flop 301 . . . also controls
whether the signal at the data-in terminal 302 or the probe-in
terminal 303 is passed onto the probe-out terminal 305. In this
manner, data from another probe point which is connected to
the probe-in terminal 303 are selectively passed onto the probe-
out terminal 305.
Id. at 8:15-21.
The description of connector circuit 310 does not state that the probe
signals are selected for capture during operation of the connector circuit in
its “normal mode” or during “normal operation” of the IC. However, this
appears to be the case. Furthermore, this conclusion is consistent with the
description of block scan connector circuit 320, which is depicted in
Figure 4b, reproduced below.

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Figure 4b is “a circuit diagram of a block scan connector for scan strings for
observing test points inside a block along a scan chain.” Id. at 3:65-67
(emphasis added). As noted above, a scan string 403 is formed by serially
connecting a plurality of block scan connector circuits 320. Id. at 8:28-29.
Block scan connector circuit 320 provides an interstitial connection between
internal elements of a block 106. Id. at 8:35-38.
Like block I/O connector circuit 310 (Fig. 4a), block scan connector
circuit 320 (Fig. 4b) in “normal operation of the IC” provides a “simple
path” between its data-in and data-out terminals: “In the normal operation of
the IC 100, the connector circuit 320 is a simple path between the internal
elements in the block 106.” Id. at 8:38-40 (emphasis added). Also like
block I/O connector circuit 310, block scan connector circuit 320 has probe-
in and probe-out terminals (313 and 315). Id. at 8:66-9:1. The probe signals
are selected for capture by connector circuit 320 while it is providing a
simple path or “simple conduit” between data-in and data-out terminals 312
and 317), i.e., during normal operation of the IC:
The connector circuit 320 acts as a simple conduit for signals
within the block 106. At the same time, the previously scanned-
in signal, which appears in the scan-slave section, selects
whether signals at the data in terminal 312 or the output from
another probe point which has been connected to the probe-in
terminal 313 is to be passed onto the probe-out terminal 315.
A probe string 402 is created. Of course, if an internal scan
string 403 need not be connected to a probe string 402, the
multiplexer 319 can be eliminated from the circuit 320.
Id. at 8:63-9:3 (emphasis added).
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The circuitry for capturing the selected probe signals is depicted in
Figure 9a, which is reproduced below.

Figure 9a shows an embodiment of the analysis engine 215 which, under the
control of the microprocessor 211, captures “logic signals” (i.e., probe
signals) from test bus 104. Id. at 10:25-28.
This is achieved by first setting either the scan flip-flops 301 of
the block I/O connector circuits 310 (FIG. 4a) or the scan flip-
flops 311 of the block scan connector circuit[s] 320 (FIG. 4b)
so that a boundary connection or an internal point connection of
the target block 106 is selected for probing, respectively. . . .
The multiplexer 421 and the multiplexer 422 in the test bus
connector 401 (FIG. 3a) are controlled by the SPU 101 so that
the signals on the probe string 402 are passed along to the test
bus 104. Finally, all remaining test bus connector circuits 401
along the same bit line of the test bus 104 are controlled by the
SPU 101 so that they pass the probe signals along test bus 104.
This allows the selected probe signal to arrive at the analysis
engine 215 where it is captured for subsequent off-line analysis.
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Id. at 10:28-46. The input terminals of a plurality of flip-flops 805, one for
each bit line of the test bus 104, form the “input port 80[1]” of the analysis
engine 215. Id. at 10:46-48. The output terminal of each flip-flop 805 is
connected to the input terminal of a respective variable First-In-First-Out
shift register (FIFO) 804. Id. at 10:51-53. Figures 9b-9d and 10, not
reproduced below, show the circuitry employed to analyze the captured
probe signals. Id. at 10:25-12:42.
Based on the above descriptions of connector circuits 310 (Fig. 4a)
and 320 (Fig. 4b), we find that connector circuit 310, when operating in “test
mode,” can use its data-in and data-out terminals 302 and 307 to load test
signals into or retrieve test signal results from a logic block. When
connector circuit 310 is operating in “normal mode” (i.e., during “normal
operation” of the IC), connector circuit 310 (1) provides a” simple path”
between data-in and data-out terminals 302 and 307 and also (2) can use
probe-in and probe-out terminals 303 and 305 (and multiplexer 309) to
select probe signals for capture and analysis.
We find that the descriptions of connector circuits 310 and 320 do not
identify or discuss the input data that is or can be applied to the logic blocks
during normal operation of the IC, when the logic blocks are generating
probe signals for capture and analysis. As explained below, the Examiner
found that Col. 14, Lines 22-45 describe applying “test data” to the logic
blocks during “normal system operations” in order to generate probe signals
for capture and analysis and that the terms “normal system operations” in
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Col. 14, Lines 22-45 and “normal system operation” in claims 1 and 4
therefore do not preclude the application of test data to the IC.

2. Col. 14, Lines 22-45
The paragraph at column 14, lines 22-45 (i.e., Col. 14, Lines 22-45)
reads in its entirety as follows:
In one mode of operation of the IC 100 shown in FIG. 1b,
the human engineer may use the diagnostics console 103 to
initialize both of the system logic and the SPU 101. In this
manner, the SPU 101 may be programmed to perform logic
analyzer functions and specific probe points may be enabled so
that a history of data values appearing at the selected probe
points can be captured by SPU 101. Additionally, the trigger
logic shown in FIGS. 9 and 10 may be programmed to select a
desired trigger event in order to stop the data capture
operations. Next, the diagnostics console 103 invoke[s] the IC
100 to execute its normal system operations. If and when the
selected trigger event is detected and the analysis engine 215
has captured the required data, the diagnostics console 103
instructs the SPU 101 to transfer the captured data values out of
the IC 100 and into the diagnostics console 103 where the data
may be formatted and presented for analysis and interpretation.
The diagnostics console 103 and the SPU 101 can constrain
some of the signals on one or more test wrappers 102 in order
to affect the behavior of the IC 100 and perform logic analysis
under these conditions. For example, this approach may be
useful to determine how the overall behavior of the IC 100 is
affected when some of the functionality of any one of the
blocks 106 is disabled.
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’301 patent 14:22-45 (emphasis added). Patent Owner (P.O. Appeal Br. 10)
and Requester (Req. Resp’t Br. 6) agree that Col. 14, Lines 22-45 must be
interpreted in light of what Requester refers to as the “two subsequent
paragraphs,” which read as follows:
In a different mode of operation automatic test equipment
(ATE) may access the IC 100 through its TAP interface 217 in
order to initialize the SPU 101 so that internal scan strings 403
and test wrappers 102 are loaded with predetermined test
values. The response of the blocks 106 is observed using the
scan strings 403 and test wrappers 102. . . .
In yet another mode of operation, it is possible to use an
in-circuit test (ICT) or similar board-level test equipment to
access the IC 100 through its TAP interface 217 in order to
instruct the SPU 101 to turn-on its external memory test
function. In this mode, patterns are generated by the SPU 101
and made to appear at specific I/O pins of the IC 100 which are
coupled to external memory.
’301 patent 14:46-54 (emphasis added).
We note that although Col. 14, Lines 22-45 do not characterize the
constraining of test wrapper signals as resulting in isolation of a portion of
the IC, the Examiner and Patent Owner make such a characterization. See
RAN 62 (“Constraining the signals on a test wrapper effectively isolates the
portion of the IC that corresponds to the respective test wrapper.”); P.O.
Appeal Br. 13 (“Therefore, the statements in the RAN . . . and the TPR
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Comments . . . , that assume that normal system operations include isolating
and constraining signals to a portion of the IC, are incorrect.”).
12

As noted earlier, the Examiner found that “[t]he term ‘normal system
operation’ as used in the Patent Owner’s claims and specification is not the
same as ‘a normal mode of operation of an integrated circuit (IC)’ in the
context of a normal mode and a test mode.” RAN 62. Specifically, the
Examiner found that the “normal system operations” described in Col. 14,
Lines 22-45 include “a test mode or operating with test data” whether or not
test wrapper signals are being constrained:
The Patent Owner’s specification makes it clear that the IC can
be in a test mode or operating with test data and still be
performing “normal system operations.” At lines 22-45 of
column 14 of the [’]301 Patent, a mode is described where test
data is loaded into the IC, then the IC performs its normal
system operations, and the results of the test are later captured
and analyzed. The Patent Owner further describes that certain
elements in the system can be isolated and still the IC can
perform “normal system operation.”
Id. (emphasis added) (quoted in part at Mercer II para. 8). The
corresponding discussion in the Action Closing Prosecution is similar and
includes the following statements, which are quoted with approval by
Requester’s expert witness:

12
Requester does not characterize the constraining option as resulting in
isolation.
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The term “normal system operation” as used in the Patent
Owner[’]s claims and specification is not the same as “a normal
mode of operation of an integrated circuit (IC)” in the context
of a normal mode and a test mode. The Patent Owner[’]s
specification makes it clear that the IC can be in a test mode and
still be performing “normal system operations.” The Patent
Owner further describes that certain elements in the system can
be isolated and still the IC can perform “normal system
operation.” The term “normal system operation,” as used in the
Patent Owner’s specification also does not exclude the use of
test data.
ACP 56; Mercer II para. 8.
We understand the Examiner to have found that the “normal system
operations” described at column 14, lines 22-38 (preceding the description
of the constraining option) may involve the application of some “test data”
in response to which the logic blocks generate the probe signals to be
captured and analyzed. Thus, these test data are applied during operation of
connector circuits 310 (Fig. 4a) in “normal mode” and during “normal
operation” of the IC.
Requester likewise characterizes Col. 14, Lines 22-45 as describing
testing whether or not any test wrapper signals are being constrained:
“[T]he paragraph reproduced above [Col. 14, Lines 22-45] describes a
scenario in which the IC executes its normal system operations while the IC
is under test, and the testing can further include constraining some of the
signals to test wrappers--all within one mode of operation.” Req. Resp’t
Br. 6 (emphasis added).
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Patent Owner has not acknowledged--let alone demonstrated error in--
the Examiner’s finding that Col. 14, Lines 22-38 describe applying test data
to the logic blocks when the test wrapper signals are not being constrained.
Instead, Patent Owner treats the Examiner’s discussion of “test data” as
referring to only the use of constrained test wrapper signals:
[T]he statements in the RAN (page 62, “[t]he Patent Owner’s
specification makes it clear that the IC can be in a test mode or
operating with test data and still be performing ‘normal system
operations,’” [)] and the TPR Comments (page 3, “normal
system operation is not necessarily exclusive of test mode”),
that assume that normal system operations include isolating
and constraining signals to a portion of the IC, are incorrect.
P.O. Appeal Br. 13 (emphasis added).
13
Dr. Khoche, Patent Owner’s expert
witness, likewise treats the Examiner’s discussion of “test data” as referring
to only the use of constrained test wrapper signals:
The “overall behavior of the IC 100 . . . when some of the
functionality of any one of the blocks 106 is disabled” (C14:43-
45) is not “normal” system operation, and the [’]301 patent
specification does not describe it as such. However, the only
mode set out in the independent claims of the [’]301 patent is
the normal mode where the service processor unit performs
capture and analysis of system operation signals during normal
system operation. Thus, the claimed “normal system operation”
does not produce test signals but instead relates to signals
produced by the integrated circuit during its normal system
operation.

13
The cited “TPR Comments” are COMMENTS BY THIRD PARTY
REQUESTER PURSUANT TO 37 CFR 1.951, filed September 20, 2012.
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Khoche II para. 15.
For the above reasons, Patent Owner has not shown error in the
Examiner’s finding that the “normal system operations” described in lines
22-38 of column 14 include the application of test data to the IC.
However, in the interest of completeness we will also consider whether the
use of constrained test wrapper signals constitutes testing that occurs during
“normal system operations.”
As noted above, Requester contends that the constraining of test
wrapper signals constitutes testing. See Req. Resp’t Br. 6 (“testing can
further include constraining some of the signals to test wrappers”) (emphasis
added). Specifically, Requester argues that “system operation signals are
produced during testing if the subsystem under test is in normal system
operation” (Req. Resp’t Br. 7) (emphasis added), with the result that “normal
system operation does not exclude operation when the logic under test is not
connected to other logic blocks.” Id. Thus, we understand “subsystem” as
used by Requester and by Patent Owner (see infra) to refer to the logic
blocks that are connected to each other or to other circuitry by unconstrained
test wrapper signals.
Patent Owner concedes that the use of constrained test wrapper
signals constitutes testing but denies that such testing is part of “normal
system operations”:
The specification further describes that in the mode of
operation where the human engineer uses the diagnostics
console, there are two other modes - a first mode relating to
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operations occurring during normal system operation
(’301 Patent, 14:24-38) and a second [i.e., constraining] mode
occurring during test (’301 Patent, 14:38-45).
P.O. Reb. Br. 6. More particularly, Patent Owner contends that the
constraining option cannot be part of “normal system operations” because
this phrase requires that all of the test wrappers (including all of their
connector circuits 310) be operating in “normal” (i.e., “simple path”) mode:
The “overall behavior of the IC 100 . . . when some of the
functionality of any one of the blocks 106 is disabled” (Col. 14,
lines 43-45) is not “normal” system operation, and the [’]301
patent specification does not describe it as such.” The
specification states, “In the normal operation of the IC, the
connector circuit 301 provides a simple path between the block
106 and the rest of the IC 100” (Col. 7, lines 43-45 (emphasis
added)), and in “normal mode,” there is “normal operational
signal flow.[”] (Col. 8, lines 9-10). As those portions of the
specification describe, during “normal operation” of the
integrated circuit, the logic blocks are connected with the rest of
the integrated circuit so that normal system operation signals
pass through to and from the logic blocks.
P.O. Appeal Br. 13. See also P.O. Reb. Br. 7 (“‘Normal system
operation[s]’ refers to the normal execution of the entire integrated circuit
system, IC 100, not some ‘subsystem.’ (See ’301 Patent at 14:31-32)[.]”)).
We are not persuaded by Patent Owner’s argument that “normal
system operations” in Col. 14, Lines 22-45 would have been understood to
require that all of the connector circuits 310 in all of the test wrappers of the
IC be operating in “simple path” mode. This argument overlooks the fact
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that “simple path” operation is only one aspect of the “normal mode” of
operation of connector circuits 310; these connector circuits when operating
in “normal mode” also perform the function of selecting probe signals for
capture and analysis.
In our view, it is more reasonable to interpret “normal system
operations” in Col. 14, Lines 22-45 to mean that the connector circuits 310
are performing their probe signal selection function. The reason is that lines
22-38 of column 14 describe capturing data values at the probe points as part
of “normal system operations” without making any mention of operation in
the “simple path” mode. The phrase “normal system operations” therefore
refers to this probe signal selection function whether or not any test wrapper
signals are being constrained. When test wrapper signals are being
constrained, this probe signal selection function is performed in order to
“determine how the overall behavior of the IC 100 is affected when some of
the functionality of any one of the blocks 106 is disabled.” ’301 patent
14:42-45.
Consequently, we are not persuaded that “normal system operations”
in Col. 14, Lines 22-45 would have been understood to preclude the use of
constrained test wrapper signals, which Patent Owner concedes constitutes a
type of testing. P.O. Reb. Br. 6. Furthermore, as explained above, Patent
Owner has not persuaded us of error in the Examiner’s finding that the
“normal system operations” that are described at column 14, lines 22-38 and
do not include the use of constrained test wrapper signals involve the
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application of “test data.” Thus, for both of these reasons, we are not
persuaded that the phrase “normal system operations” in Col. 14, Lines 22-
45 precludes the application of test data or operation in a test mode.

3. Claims 1, 2, 4, and 5
Even assuming for the sake of argument that Patent Owner had shown
that “normal system operations” as used in Col. 14, Lines 22-45 would have
been understood to preclude the application of test data, it is not permissible
to read limitations from examples given in the specification into the claims.
Phillips, 415 F.3d at 1323.
Dependent claim 2, on which Patent Owner relies, reads as follows:
2. An integrated circuit as in claim 1, wherein, in a
second mode of operation, said service processor unit performs
tests on one or more of said one or more logic blocks through
said test bus interface.
Claims App. (Req. Appeal Br. 11). Claim 5 is identical but depends on
claim 4. Patent Owner argues:
Claims 2 and 5 provide further evidence that the “first mode”
recited in claims 1 and 4, in which the SPU performs capture
and analysis of system operation signals during “normal system
operation” is different from “a second mode of operation,” in
which the service processor unit “performs tests on one or more
of said one or more logic blocks.” (See [’]301 patent,
claims 2, 5).
P.O. Appeal Br. 12. We note that “[w]hile it is true that dependent claims
can aid in interpreting the scope of claims from which they depend, they are
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only an aid to interpretation and are not conclusive.” North American
Vaccine, Inc. v. American Cyanimid Co., 7 F.3d 1571, 1577 (Fed. Cir.
1993).
Claims 1 and 4 do not provide any basis for interpreting “normal
system operation” as precluding the application of test data or precluding
operation in a test mode. These claims do not recite an element that has
“normal” and “test” modes of operation, let alone recite the characteristics of
these modes and their relationship to “normal system operation.” Although
claims 1 and 4 each recite “a service processor unit to perform test and
debug operations of said logic blocks of said integrated circuit” (emphasis
added), they do not recite or imply that “normal system operation” excludes
these “test and debug operations” or the application of test data to the recited
“one or more logic blocks.” Furthermore, although it is clear from the
language “capture and analysis of system operation signals during normal
system operation” (claims 1 and 4) that the “capture and analysis of system
operation signals” occurs during “normal system operation,” these claims do
not indicate what, if anything, is precluded by “normal system operation.”
The foregoing conclusions regarding the interpretation of claims 1
and 4 are not altered when these claims are considered in light of claims 2
and 5. Neither of claims 2 and 5 requires that service processor unit
performs its second mode of operation (i.e., “perform[ing] tests on one or
more of said one or more logic blocks through said . . . bus interface”)
outside of “normal system operation.” Claims 1, 2, 4, and 5 therefore are
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broad enough to permit both modes of operation to be performed during
“normal system operation.” Thus, these claims are broad enough to permit
the service processor unit to perform its first mode of operation (i.e.,
“perform[ing] capture and analysis of system operation signals”) at the same
time that it is performing its second mode of operation (i.e., “perform[ing]
tests on one or more of said one or more logic blocks through said . . . bus
interface.”). We therefore agree with Requester that “the modes of claims 1
and 2 are not mutually exclusive.” Req. Resp’t Br. 9.
We also note that dependent claims 13 and 22, which directly depend
on claims 1 and 4, respectively, recite testing without further specifying that
the testing occurs outside of “normal system operation”:
13. An integrated circuit as in Claim 1, wherein:
the control unit controls loading test signals for the one
or more logic blocks, and retrieving captured test signal results
from the one or more logic blocks.
22. An integrated circuit as in Claim 4, wherein:
the control unit controls loading test signals for the one
or more logic blocks, and retrieving captured test signal results
from the one or more logic blocks.
Claims App. (Req. Appeal Br. 14-15).
For the above reasons, we are unpersuaded by Patent Owner’s
argument that “[s]ignals produced under ‘normal system operation[]’ do not
include signals produced in response to predetermined test data.”
P.O. Appeal Br. 12 (footnote omitted). Therefore, Patent Owner has not
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demonstrated error in the Examiner’s conclusion that “the term ‘normal
system operation’ does not exclude the IC or portions of the IC from being
under test or in a test mode.” RAN 63.

III. THE EXAMINER’S REJECTIONS BASED ON FRANKLIN
A. The Rejection of Claims 1-6, 9, 10, 12-16, and 20-25 for Anticipation by
Franklin.
The only claims that are specifically argued with respect to this
ground of rejection are claims 1 and 4. The other claims rejected on this
ground are treated as standing or falling with claims 1 and 4. See P.O.
Appeal Br. 23 (“Franklin does not anticipate independent claims 1 or 4.
Claims 2-3, 5-6, 9-10, 12-16, and 20-25 are therefore allowable at least by
virtue of their dependency from claim 1 or claim 4 and because they recite
additional features.”). Patent Owner does not identify or discuss these
“additional features.”
We begin by addressing Patent Owner’s argument that in Ex parte
Reexamination No. 90/011,584, which involved the grandparent ’865 patent,
the same Examiner who is handling this inter partes proceeding determined
that the claim phrase “normal system operations” in claim 19 patentably
distinguished that claim from both Zorian and Franklin. P.O. Appeal Br. 24
(citing “Notice of Intent to Issue a Reexamination Certificate” mailed
November 2, 2012). It is well settled that appealed claims must be judged
on their own merits and not on the basis of a comparison with other claims
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that have been allowed. In re Margaroli, 318 F.2d 348, 352 (CCPA 1963).
See also In re Willis, 455 F.2d 1060, 1062-63 (CCPA 1972) (“What the
Patent Office has allowed in previous cases is not binding in subsequent
cases, especially when different factual situations are involved.”); In re
Riddle, 438 F.2d 618, 620 (CCPA 1971 (rejecting applicant’s argument that
“the allowance of a claim by an examiner in a patent is a bar to the rejection
of a claim in an application to substantially the same invention on
substantially the same art considered in the patent prosecution.”).
Turning now to the merits of the rejection, Franklin provides an
examination of various BIST (built-in self-testing) schemes. Franklin, title
and 45 col. 2. Franklin explains that “[a]n examination of BIST schemes
indicates that approaches based on test architectures rather than on test
algorithms are more versatile and will likely predominate in the future.”
Id. at 45 col. 2. One motivation for using BIST is that
the BIST logic incorporated in a chip can be used for both
manufacture testing and in-circuit testing. If the implemented
algorithm’s test length is sufficiently small, the same BIST
logic can even be used for testing RAMs during computer
power-on, as part of the CPU’s self-test procedures.
Id. at col. 3 (emphasis added). However, Franklin adds, in a statement relied
on by Patent Owner, that “[c]urrent BIST implementations cannot, however,
be used for testing when the chip contains useful data.” Id. In this same
vein, Franklin states that “[w]hen a memory chip is being used in a system
(that is, when the chip contains valid data), it cannot be tested on line
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because the test procedure might destroy the memory contents.” Id. at 55
col. 3.
Franklin further explains that “[c]onceptually, the BIST logic can be
divided into four parts: control logic, address-generation logic, data-
generation and response-verification logic, and test-trigger logic.” Id. at 51
col. 1.
Figure 6 of Franklin is reproduced below.

Franklin 51. As stated in the caption thereto, Figure 6 is a generic block
diagram of “random-logic-based” BIST logic for RAMs. The control logic
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initiates and stops testing and supervises the control flow of the test
algorithm. Id. at 51 col. 2. The data-generation logic produces the test
pattern(s) to be written in the cells. Id. at 51 col. 3. Given a test
architecture, different strategies can be used for data generation as well as
response verification. Id. at 51-52. In an SASB (single-array single bit
14
)
architecture, the correctness of the read values can be verified either by
comparing them against the expected values or by signature analysis, with
direct comparison being superior because it can locate single stuck-at faults.
Id. at 52 cols. 1-2.

14
Franklin 50 col. 2.
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The sole figure appearing at page 53 of Franklin is reproduced below.

Id. at 53. As stated in the caption, this figure is a block diagram of
“microcode-based” BIST logic for the row/column weight-sensitive fault
test. The Examiner (RAN 25) reads the “wherein” clauses of claims 1 and
4 on the following passage in Franklin:
Test trigger logic. All BIST RAMs have a normal mode in
which the BIST logic is inactive and one or more test modes in
which the BIST logic is active. The test modes can be entered
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using overvoltages, extra package pins, or unique timing
sequences with such inputs as Chip Enable, Write Enable, Row
Address Strobe, and Column Address Strobe.
Franklin 53-54. The Examiner reads the claimed “normal system operation”
on the test modes: “As discussed above, [claim 1] can be reasonably
interpreted as the logic blocks generating signals while performing their
normal system operation and the logic block can be using test data while
performing those operations.” RAN 64 (emphasis added). In the preceding
page, which addresses anticipation by Zorian, the Examiner more
particularly explains that “the term ‘normal system operation’ does not
exclude the IC or portions of the IC from being under test or in a test mode.”
Id. at 63 (emphasis added).
According to Patent Owner, Franklin fails to anticipate the claims
because
Franklin describes BIST implementations whereby test patterns
are generated by the BIST controller and test responses are read
out and compared to known or expected values. The test
response signals are not system operation signals because none
of these signals relate to signals generated through normal
system operation of the IC. Instead, the signals are in response
to test signals applied to the memory cell of the integrated
circuit.
P.O. Appeal Br. 22 (footnotes omitted). This argument is unpersuasive
because, for the reasons given above, the claim phrase “normal system
operation” does not preclude the application of test data to the IC.
Patent Owner also makes the following argument:
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“[W]hen the memory chip contains useful data, i.e., in its
normal mode of operation and generating system-operation
signals, Franklin’s BIST methodology is unusable. Franklin
also acknowledges that “[w]hen a memory chip is being used in
a system (that is, when the chip contains valid data), it cannot
be tested on line because the test procedure might destroy the
memory contents.”
P.O. Appeal Br. 23 (footnotes omitted) (quoting Franklin 45 col. 3 and
55 col. 3). Accord, Khoche II paras. 21-22. This argument is unpersuasive
because it incorrectly assumes that the claim phrase “normal system
operation” requires the recited “one or more logic blocks” to contain useful
data. We agree with Dr. Mercer that the above-quoted admonitions in
Franklin
could be more properly understood to suggest: “If you plan to
use BIST to self-test a memory in a system deployed to the
field, be sure that you do not use the resulting contents of the
tested memory - because those contents will be the result of a
self-test, and they would not be useful for system booting.”
Mercer II para. 23.
For the reasons given above, Patent Owner has not shown error in the

Examiner’s conclusion that the claim phrase “normal system operation” is
broad enough to read on Franklin’s test modes.
The rejection of claims 1-6, 9, 10, 12-16, and 20-25 for anticipation
by Franklin accordingly is sustained.

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B. The Rejection of Claims 7, 8, and 17-19 for Obviousness over Franklin in
View of Zorian
Patent Owner’s only argument against this rejection is that “[c]laims
7-8 and 17-19 are . . . allowable at least by virtue of their dependency from
claim 1 or claim 4 and because they recite additional features.” P.O. Appeal
Br. 24. These additional features have not been identified or discussed.
The rejection of claims of claims 7, 8, and 17-19 for obviousness over
Franklin in view of Zorian is therefore sustained.

C. The Rejection of Claim 11 for Obviousness over Franklin in view of
Sauerwein
Patent Owner treats this rejection of claim 11 as standing or falling
with the rejection of claim 1 for anticipation by Franklin:
Franklin does not disclose an integrated circuit, “wherein, in a
first mode of operation, said service processor unit performs
capture and analysis of system operation signals during normal
system operation through said test bus interface”, as recited in
Claim 1, from which Claim 11 depends. Sauerwein was not
cited for disclosing, nor does it disclose[,] the elements missing
in Franklin. Thus, even if combined, the resulting system
would still not teach each of the features of Claim 11.
P.O. Appeal Br. 23-24.
The rejection of claim 11 for obviousness over Franklin in view of
Sauerwein is sustained.
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IV. REQUESTER’S PROPOSED BUT UNADOPTED
REJECTIONS BASED ON FRANKLIN
A. The Proposed Rejection of Claims 1-6, 9, 10, 12-16, and 20-25 for
Obviousness Based on Franklin (Proposed Rejections #4 and #10)
1. Claims 1-6 (Proposed Rejection #4)
Regarding claims 1-6, Requester argues:
It was error not to adopt the rejection of claims 1-6 as
obvious over Franklin. As noted by the RAN, Franklin
anticipates each element of claims 1-6 of the [’]301 patent. As
anticipation is the “epitome of obviousness,” [In re] Kalm,
378 F.2d [959,] 962 [(CCPA 1967)], Franklin also renders
claims 1-6 obvious under 35 U.S.C. § 103(a).
. . . Furthermore, to the extent that PO may argue lack of
anticipation, the similarities between the disclosure of Franklin
and claims 1-6 of the [’]301 patent are such that the
“differences between the subject matter sought to be patented
and the prior art are such that the subject matter as a whole
would have been obvious.” See 35 U.S.C. § 103(a).
Req. Appeal Br. 7 para. 2.
We are not persuaded by either of these arguments. The “epitome of
obviousness” rationale described in Kalm merely provides a basis for
sustaining a rejection for obviousness under 35 U.S.C. § 103(a). It does not
provide any authority for using a finding of anticipation as a basis for
rejecting a claim for obviousness under 35 U.S.C. § 103(a). The assertion
that the claimed subject matter would have been obvious from Franklin is
unsupported by (i) the identification of any admitted or possible differences
between the claims and Franklin and (ii) an explanation of why such
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differences do not patentably distinguish the claims from Franklin. See In re
Kahn, 441 F.3d 985, 988 (Fed. Cir. 2006) (“[R]ejections on obviousness
grounds cannot be sustained by mere conclusory statements; instead, there
must be some articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness.”).
The Examiner’s decision not to adopt the proposed rejection of claims
1-6 for obviousness based on Franklin therefore is sustained.

2. Claims 9, 10, 12-16, and 20-25 (Proposed Rejection #10)
As support for this proposed rejection, Requester repeats the
arguments made in support of Proposed Rejection #4 for the obviousness of
claims 1-6 over Franklin. Req. Appeal Br. 8, para. 6.
The Examiner’s decision not to adopt the proposed rejection of claims
9, 10, 12-16, and 20-25 for obviousness based on Franklin is sustained.

B. The Proposed Rejection of Claims 9, 10, 14-16, 20, 23, and 25 for
Obviousness Based on Franklin in View of Sauerwein (Proposed
Rejection #11)
As support for this proposed rejection, Requester relies on the
arguments made in support of Proposed Rejection #4 for obviousness of
claims 1-6 over Franklin and asserts, without providing the necessary
supporting analysis, that any differences between claims 9, 10, 14-16, 20,
23, and 25 and Franklin would have been rendered obvious by Sauerwein.
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The Examiner’s decision not to adopt the proposed rejection of
claims 9, 10, 14-16, 20, 23, and 25 for obviousness based on Franklin in
view of Sauerwein therefore is sustained.

V. THE EXAMINER’S REJECTIONS BASED ON ZORIAN
A. The Rejection of Claims 1-10 and 12-26 for Anticipation by Zorian
Regarding this ground of rejection, Patent Owner specifically argues
only claims 1 and 4. See P.O. Appeal Br. 21 (“Claims 2-3, 5-10, and 12-26
are allowable at least by virtue of their dependency from independent claim
1 or independent claim 4 and because they recite additional features.”).
These “additional features” are not identified or argued.
Patent Owner’s arguments against anticipation by Zorian are based on
the claim phrase “normal system operation” and other claim limitations.
Zorian “discusses in general the challenges in testing core-based
system-chips and describes their corresponding test solutions.” Zorian 191,
Abstract. Zorian describes core test access in an SOC (system-on-chip
15
)
and explains that in order to establish an electronic access mechanism, two
basic elements need to be incorporated into the design: (i) a set of access
paths and (ii) a mode control network for enabling and disabling the desired
access paths. Id. at 191 cols. 1-2.

15
Zorian 191 col. 1.
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The SOC test is a single composite test comprised of individual core
tests of each core, a UDL test, and a test of their interconnects. Id. at 194
col. 2, 1st para. Each individual core or UDL test may involve surrounding
components, and certain peripheral constraints (e.g. safe-mode, low power
mode, bypass mode) are often required, necessitating corresponding access
and isolation modes. Id.
Figure (3) (hereinafter “Figure 3”) of Zorian is reproduced below.

Id. at 193. Figure 3 is a block diagram that, as stated in the caption thereto
and the text therein, shows a system-on-chip with embedded core
accessibility. Accessibility is provided by access paths in the following
manner:
1. Access Path: An access path is meant to connect a core
periphery (e.g. input, output, or bidirectional) to the assigned
test resource block. Figure (3) demonstrates three access paths
connecting core inputs Pl, P2, and P3 to three possible test
resources T1, T2, T3. . . . N1, N2, and N3 are normal mode
inputs to the Embedded Core.
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The Peripheral Access block contains the necessary DFT
structure for all core peripheries to switch between normal and
test modes.
Id. at 193 col. 2 (brackets in original).
Figure 4 of Zorian is reproduced below:

Figure 4, as stated in the caption, shows embedded cores with peripheral
access.

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Figure 5 is reproduced below.

Figure 5, as stated in the caption, shows a system-on-chip with core internal
test, peripheral access, and a core test interface. A CTAP (Core Test Access
Port)
provides a standard serial communication interface that all
internal cores must have, at a minimum. The CTAP requires a
minimum number of internal bussing signals and IC pins. It
can be used by itself to support internal core testing and
external core testing based on known test methods such as scan,
boundary scan, BIST.
Id. at 198, col. 2, last para.
The Examiner reads the recited “one or more logic blocks” on “for
instance, the USB, the DSP, or the DMA” of Figures 4 and 5 (RAN 9) and
reads the “wherein” clause on Zorian as follows:
[S]ee page 193, col. 2, wherein “In addition to the normal and
core internal test modes, a System-on-chip often requires
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several other test related modes.”; also see page 198, col. 2
through page 199, col. 1, wherein “[The CTAP] can be used by
itself to support internal core testing and external core testing
based on known test methods such as scan, boundary scan,
BIST. The CTAP can be used to enable additional internal
bussing signals and/or IC pins to expand core testing to meet a
particular core provider’s private test method(s). ... Among its
functions it needs to place the core in a safe-mode, such that its
outputs do not affect other cores and that arbitrary values may
be placed on its inputs.”
Id. at 13 (brackets altered). The Examiner more particularly explained that
the claim phrase “normal system operation” reads on Zorian’s test modes:
Patent Owner is arguing that Zorian does not operate in a
“normal mode”. As discussed above, the term “normal system
operation” does not exclude the IC or portions of the IC from
being under test or in a test mode. As noted above, the Patent
Owner’s specification allows for the loading, executing, and
evaluating of test data, therefore the test patterns of Zorian can
properly be construed as the claimed system operation signals.
Id. at 63.

1. Whether Zorian Describes Capturing and Analyzing System
Operation Signals Generated “During Normal System Operation”
Patent Owner’s principal argument against the rejection is that “[t]he
signals disclosed in Zorian’s core internal testing methodology represent test
pattern response signals and are not signals that occur during normal system
operation of the IC, but instead are signals that contain values in response to
the applied test pattern.” P.O. Appeal Br. 14 (footnote omitted). This
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argument is unpersuasive because, for the reasons given above, the claim
phrase “normal system operation” does not preclude the application of test
data to the recited “one or more logic blocks” or operation in a test mode.
As a result, the claim phrase “normal system operation” reads on Zorian’s
Figure 3 example when it is operating in a “test” mode.

2. Whether Zorian Discloses Generating System Operations Signals
at One or More System Clock Rates (Claims 1 and 4)
The Examiner (RAN 9) reads the claim language “generating one or
more system operation signals at one or more system operation clock rates”
on the following statement in Zorian: “In realistic examples often a
combination of serial and parallel access cells are used for a given core,
where the data patterns are applied through the serial ring, whereas the
clocks and control signals are asserted via parallel access.” Zorian 197 col.
1, 2d full para. (emphasis added). Patent Owner argues:
The clocks disclosed in Zorian are not disclosed as
system operation clock rates. The clocks mentioned in Zorian
are input to the core under test. Further, to the extent that
Zorian discloses any system operation signals, such signals are
not generated at the rates of the cited clocks. Zorian’s clocks
are “asserted via parallel access” for purposes such as clocking
in test data. Test “data patterns applied ... through the serial
ring” are not system operation signals. The signals are test
data. Further, there is no disclosure relating the asserted signals
to the components asserted as the logic blocks (i.e., USB, DSP,
DMA) that must (according to the claim) generate such signals.
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P.O. Appeal Br. 17-18 (footnotes omitted).
We agree with Requester that clock signals “asserted in realistic
testing” will “necessarily have a rate and this rate is at least one of the clock
rates in the system.” Req. Resp’t Br. 11. As a result, Zorian’s logic blocks
will respond to these clock signals and the applied data patterns by
generating system operation signals at one or more system clock rates, as
required by claims 1 and 4.

3. Whether Zorian Discloses an SPU That Includes a Control Unit
The Examiner, referring to Figure 5, reads the recited “service
processor unit” (SPU) on a CTAP (Core Test Access Port) and the recited
“control unit” on the peripheral access blocks. ACP 8-9; RAN 10-11.
Patent Owner contends that “claim 1 requires that the control unit be
part of the service processor unit” and that “[i]t is clear from both the text of
Zorian (which discloses no such relationship) and from Zorian, Figure 5 . . .
that the Peripheral Access blocks (bold lines shown in Zorian Figure 5) are
not part of the CTAP . . . .” P.O. Appeal Br. 18.
The Examiner disagrees, stating that “the claim does not require the
control unit to be within the service processor unit.” ACP 61. Requester
defends the Examiner’s claim interpretation as follows:
The Examiner is correct that under the broadest
reasonable interpretation of the claim language, claims 1 and 4
do not require that the service processor unit include a control
unit, a buffer memory, an analysis engine, a BIST engine, or a
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system bus interface. It is not clear that further comprising
modifies service processor unit, and in fact, it is more likely
that further comprising modifies said integrated circuit (the
noun which immediately precedes further comprising).
Specifically, there is no recitation in the claims regarding what
structures the service processor initially comprises; therefore
reciting what the service processor further comprises would be
premature. However the claim language regarding the IC does
set forth initial structures (one or more logic blocks and the
service processor) so to set forth what the IC further comprises
makes more sense from a textual standpoint. Also, PO could
have phrased the above-recited passage to say, “said service
processor unit further comprising,” but chose a broader and
more ambiguous phrasing instead. Thus, Requester’s reading is
correct, as it complies with the broadest reasonable
interpretation used by the USPTO
Req. Resp’t Br. 10. We disagree with the Examiner’s and Requester’s claim
interpretation because it fails to accord sufficient weigh to the claims’
paragraph structure, punctuation, and use of “and” at the end of the first
paragraph in each claim, of which claim 1 reads in relevant part as follows:
1. An integrated circuit comprising:
one or more logic blocks generating one or more system
operation signals at one or more system operation clock rates;
and
a service processor unit to perform test and debug
operations of said logic blocks of said integrated circuit, further
comprising:
a control unit; . . . .
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Claims App. (Req. Appeal Br. 11) (emphasis added). We therefore agree
with Patent Owner that the language of claims 1 and 4 requires the recited
“control unit” (and other elements) to be part of the “service processor unit.”
Furthermore, this conclusion is based on the claim language itself and thus
does not involve importing a limitation into the claims from Figure 2 of the
’301 patent, which depicts SPU 101 as including, inter alia, microprocessor
211, which is described as a “control unit.” ’301 patent 6:33-34.
Nevertheless, Patent Owner has not explained, and it is not apparent, why
the recited “service processor unit” cannot be read on the Zorian subject
matter the Examiner identifies as corresponding to the service processor unit
plus the subject matter identified as corresponding to its recited components,
including the control unit.

4. Whether Zorian Discloses an SPU That Includes an Analysis
Engine
The Examiner (RAN 11) reads the recited “analysis engine” on the
following sentence in Zorian: “Furthermore, diagnostic modes are often
very critical to the production of SOC. They are required to identify failed
cores in some cases to determine the internal failures to each core.” Zorian
194 col. 2, 3d full para. Patent Owner argues that “[t]he disclosure of
‘diagnostic modes’ is not a disclosure of an analysis engine that is part of a
service processor unit in the integrated circuit.” P.O. Appeal Br. 20. For
reasons like those given above, we agree with Patent Owner that the recited
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“analysis engine” is part of the “service processor unit.” However, Patent
Owner has not explained, and it is not apparent, why the recited “service
processor unit” cannot be read on the Zorian subject matter the Examiner
identifies as corresponding to the service processor unit plus the subject
matter identified as corresponding to its recited components, which include
the analysis engine.
5. Conclusion
The rejection of claims 1-10 and 12-26 for anticipation by Zorian is
sustained.
B. The Rejection of Claim 11 for Obviousness over Zorian in view of
Sauerwein
Claim 11 depends from claim 1 through claim 9. Patent Owner treats
this rejection of claim 11 as standing or falling with the rejection of claim 1
for anticipation by Zorian. See P.O. Appeal Br. 21, sec. d (“Sauerwein was
not cited for disclosing, nor does it disclose the elements missing in Zorian.
Thus, even if combined, the resulting system would still not render obvious
the features of Claim 11.”).
The rejection of clam 11 for obviousness over Zorian in view of
Sauerwein is sustained for the same reasons that we have sustained the
rejection of claim 1 for anticipation by Zorian.

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VI. REQUESTER’S PROPOSED BUT UNADOPTED
REJECTIONS BASED ON ZORIAN
A. The Proposed Rejection of Claims 1-10 and 12-26 for Obviousness
Based on Zorian (Proposed Rejections #2 and #6)
1. Claims 1-6 (Proposed Rejection #2)
Requester argues that the proposed obviousness rejection of claims 1-
6 based on Zorian should be entered because (i) anticipation is the “epitome
of obviousness” and (ii) the differences between Zorian and claims 1-6 are
such that the claimed subject matter would have been obvious. Req. Appeal
Br. 6-7, sec. 1. These arguments are unpersuasive for the reasons given
above in the discussion of Proposed Rejection #4 of claims 1-6 for
obviousness over Franklin.
The Examiner’s decision not to adopt the proposed rejection of
claims 1-6 for obviousness based on Zorian is therefore sustained.

2. Claims 7-10 and 12-26 (Proposed Rejection #6)
Regarding these claims, Requester states:
This proposed rejection should have been adopted for the same
reason that RAN Ground 2 should have been adopted.
Furthermore, to the extent that PO may argue lack of
anticipation, the similarities between the disclosure of Zorian
and added claims 7-10 and 12-26 are such that the “differences
between the subject matter sought to be patented and the prior

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art are such that the subject matter as a whole would have been
obvious.” See 35 U.S.C. § 103(a).
Req. Appeal Br. 7, sec. 3. These arguments are unpersuasive for the reasons
given above in the discussion of the proposed rejection for the obviousness
of these claims based on Franklin.
The Examiner’s decision not to adopt the proposed rejection of claims
7-10 and 12-26 for obviousness based on Zorian is sustained.

B. The Proposed Rejection of Claims 9, 10, 14-16, 20, 23, and 25 for
Obviousness over Zorian and Sauerwein (Proposed Rejection #7)

As support for this proposed rejection, Requester relies on the
arguments made in support of Proposed Rejection #2 of claims 1-6 for
obviousness of claims 1-6 over Zorian and additionally asserts, without
providing the required supporting analysis, that any differences between
claims 9, 10, 14-16, 20, 23, and 25 and Zorian would have been rendered
obvious by Sauerwein. Req. Appeal Br. 7-8, sec. 4.
The Examiner’s decision not to adopt the proposed rejection of
claims 9, 10, 14-16, 20, 23, and 25 for obviousness over Zorian and
Sauerwein is sustained.

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C. The Proposed Rejection of Claims 12 and 21 for Obviousness over
Zorian and Franklin (Proposed Rejection #8)
As support for this proposed rejection, Requester relies on the
arguments made in support of Proposed Rejection #2 of claims 1-6 for
obviousness of claims 1-6 over Zorian and additionally asserts, without
providing the required supporting analysis, that any differences between
claims 12 and 21 and Zorian would have been rendered obvious by Franklin.
Req. Appeal Br. 8, sec. 5.
The Examiner’s decision not to adopt the proposed rejection of claims
12 and 21 for obviousness over Zorian and Franklin is sustained.

VII. CONCLUSIONS
A. The Rejections Entered by the Examiner
We sustain all of the Examiner’s rejections, which are as follows:
1. Claims 1-10 and 12-26 under 35 U.S.C. § 102(a) for anticipation by
Zorian.
2. Claims 1-6, 9, 10, 12-16, and 20-25 under 35 U.S.C. § 102(b) for
anticipation by Franklin.
3. Claims 7, 8, and 17-19 under 35 U.S.C. § 103(a) for obviousness
over Franklin in view of Zorian.
4. Claim 11 under § 103(a) for obviousness over Zorian in view of
Sauerwein.
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5. Claim 11 under 35 U.S.C. § 103(a) for obviousness over Franklin in
view of Sauerwein.

B. The Unadopted Rejections Proposed by Requester
We also sustain the Examiner’s decision not to adopt any of the
following proposed rejections of claims 1-6, 9, 10, 12-16, and 20-25:
1. Claims 1-10 and 12-26 under 35 U.S.C. § 103(a) based on Zorian
(Proposed Rejections #2 and #6).
2. Claims 1-6, 9, 10, 12-16, and 20-25 under 35 U.S.C. § 103(a) based
on Franklin (Proposed Rejections #4 and #10).
3. Claims 9, 10, 14-16, 20, 23, and 25 under 35 U.S.C. § 103(a) based
on Zorian in view of Sauerwein (Proposed Rejection #7).
4. Claims 12 and 21 under 35 U.S.C. § 103(a) based on Zorian in view
of Franklin (Proposed Rejection #8).
5. Claims 9, 10, 14-16, 20, 23, and 25 under 35 U.S.C. § 103(a) based
on Franklin in view of Sauerwein (Proposed Rejection #11).

VIII. DECISION
The Examiner’s decision that claims 1-26 are unpatentable over the
prior art is AFFIRMED.
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The Examiner’s decision not to adopt the proposed additional
rejections of claims 1-6, 9, 10, 12-16, and 20-25 is AFFIRMED.
Patent Owner’s Appeal: AFFIRMED
Requester’s Appeal: AFFIRMED

ak

For Patent Owner:

2nd Reexam Group - Novak Druce + Quigg LLP
1000 Louisiana Street
Fifty-Third Floor
Houston TX 77002

For Third-Party Requester:

Haynes and Boone, LLP IP Section
2323 Victory Avenue Suite 700
Dallas, TX 75219