Ex Parte 6777757 et al

Patent Trial and Appeal Board

Sep 10, 2014

95001468 (P.T.A.B. Sep. 10, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,468 10/14/2010 6777757 028489-000300US 7108
25096 7590 09/11/2014
PERKINS COIE LLP - SEA General
PATENT-SEA
P.O. BOX 1247
SEATTLE, WA 98111-1247
EXAMINER
ANDUJAR, LEONARDO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
09/11/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

SIDENSE CORP.
Requester and Respondent

v.

KILOPASS TECHNOLOGIES, INC.
Patent Owner and Appellant
________________

Appeal 2014-001102
Reexamination Control 95/001,468
Patent 6,777,757 B2
Technology Center 3900
________________

Before KEVIN F. TURNER, STEPHEN C. SIU, and
STANLEY M. WEINBERG, Administrative Patent Judges.

WEINBERG, Administrative Patent Judge.

DECISION ON APPEAL

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A. STATEMENT OF THE CASE
Introduction
This reexamination proceeding arose from a third party request for
inter partes reexamination filed on October 14, 2010 (Request). The patent
involved in this reexamination appeal proceeding, US 6,777,757 B2 (the
“’757 Patent”) issued to Jack Zezhong Peng, et al. on August 17, 2004.
Kilopass Technologies, Inc. (Kilopass), the Patent Owner, appeals under
35 U.S.C. §§ 134(b) and 315(a) from a final rejection of claims 1, 3-8, and
10-39.
1
Claims 2 and 9 have been canceled. App. Br. 1, 33, 35 (Claims
App’x); RAN 1. We conclude that the RAN’s statements that claim 9 has
been rejected over various combinations of prior art (RAN 7, 12) is harmless
error.
We also conclude that the following statement in the Conclusion
section of Patent Owner Kilopass’s Rebuttal Brief is a typographical error:
“For the above reasons, requester maintains that the Examiner’s findings of
patentability of claims 1, 5, 6, 12, 13, 21 and 27-36 are erroneous. The
Board should reverse the Examiner’s findings of patentability and adopt
each of the rejections proposed by Requester in Requester’s Comments.”
(emphasis omitted).
An oral hearing was held on January 22, 2014. A transcript (Tr.) was
made of record on July 17, 2014.

1
Kilopass relies on its Appeal Brief (App. Br.) filed December 18, 2012 and
its Rebuttal Brief (Reb. Br.) filed September 16, 2013. Respondent Sidense
Corp. (Sidense) relies on its Respondent Brief (Resp. Br.) filed January 18,
2013. The Examiner’s Right of Appeal Notice (RAN) was mailed
September 19, 2012.
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We have jurisdiction under 35 U.S.C. §§ 134(b) and 315(a).
We affirm-in-part.
Related Proceedings
Kilopass informs us that this inter partes reexamination proceeding is
related to litigation styled Kilopass Technologies, Inc. v. Sidense Corp.,
D. Northern District of California, case no. C10-02066 and that it was under
appeal in the U.S. Court of Appeals for the Federal Circuit at the time
Kilopass filed its Appeal Brief. App. Br. 1.
Kilopass also informs us that at the time it filed its Appeal Brief, there
were pending related inter partes reexamination of two patents in the same
family as the ‘757 Patent; specifically, Control Nos. 95/001,474 and
95/001,495.
The Invention
The invention relates to a programmable memory cell comprised of a
transistor located at the crosspoint of a column bitline and a row wordline.
The memory cell is programmed by applying a voltage potential between the
column bitline and the row wordline to produce a programmed n+ region in
the substrate underlying the gate of the transistor. Abstract.
Claim 1 is illustrative of the appealed subject matter and is reproduced
below (App. Br. 33, Claims App’x):
1. A programmable memory cell useful in a memory
array having column bitlines and row wordlines, the
memory cell comprising:
a transistor having a gate, a gate dielectric between the gate and
over a substrate, and first and second doped
semiconductor regions formed in said substrate adjacent
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said gate and in a spaced apart relationship to define a
channel region therebetween and under said gate, the gate
being formed from one of said column bitlines;
a row wordline segment coupled to the second doped
semiconductor region of the transistor, said row wordline
segment connected to one of said row wordlines; and
a programmed doped region formed in said substrate in said
channel region when said memory cell has been
programmed.

The Prior Art
US 4,876,220 Moshen Oct. 24, 1989
US 5,672,994 Au Sept. 30, 1997
US 6,396,120 B1 Bertin (Bertin ‘120) May 28, 2002
US 6,531,410 B2 Bertin (Bertin ‘410) Mar. 11, 2003
Rasras et al., Substrate Hole Current Origin After Oxide Breakdown, IEEE
2000, pp. 537-540.
The Rejections
Claims 1, 3, 5-10, 12-29, 31-35, and 37-39 stand rejected under
35 U.S.C. § 102(b) as anticipated by Moshen.
Claims 1, 3, 5-10, 12-29, 31-35, and 37-39 stand rejected under
35 U.S.C. § 103(a) as obvious over Moshen and Rasras.
Claims 1, 3-8, and 10-39 stand rejected under 35 U.S.C. § 103(a) as
obvious over Moshen and Bertin ‘410.
Claims 1, 3-8, and 10-39 stand rejected under 35 U.S.C. § 103(a) as
obvious over Moshen and Bertin ‘120.
Claims 1, 3-8, and 10-39 stand rejected under 35 U.S.C. § 103(a) as
obvious over Moshen and Au.
B. ANALYSIS
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The Anticipation Rejections
The Examiner finds that Moshen discloses a transistor having
elements 232 and 226; that is, “a p-channel transistor (depletion mode
transistor).” RAN 7-8. Without providing any supporting evidence,
Kilopass asserts that a number of concepts are “common knowledge” and
“evident” and provides attorney argument that Moshen is not a depletion
mode MOSFET. App. Br. 10-11. In the absence of evidence, these
arguments are not persuasive.
Kilopass also asserts that “[t]he present claimed invention is not a
MOSFET that operates as a traditional transistor because only the second
doped region is connected externally and first doped region is electrically
isolated from the second.” App. Br. 11. This argument is not persuasive
because it does not identify the claim(s) to which it is directed, including a
claim that recites “the second doped region is connected externally and first
doped region is electrically isolated from the second.”
Kilopass contends that claim 1 “requires a specialized transistor-like
structure that can be considered a ‘gated capacitor’” (App. Br. 8, 11) and
that, in contrast, Moshen teaches only a simple capacitor. App. Br. 9.
Claim 1 does not, however, recite a capacitor, whether gated or otherwise,
and Kilopass later agrees that “the Board should only look to the claimed
elements (when read in light of the specification) to determine if each
element is described in the prior art.” Reb. Br. 2. We therefore do not
consider whether the claimed structure can be considered to be a gated
capacitor or whether Moshen teaches a simple capacitor.
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Kilopass asserts that “[e]ven if it is accepted that Moshen teaches a
transistor, that is not what is claimed in claims 1 and 7.” App. Br. 11. We
do not understand the point Kilopass is attempting to make because claim 1
recites “a transistor having a gate . . . .”
Kilopass also contends that “the claims require that during
programming, ‘a programmed doped region is formed in said substrate’” and
that “Moshen teaches a completely different method.” App. Br. 12. As
Sidense points out, however, claim 1 is a structure claim, not a method claim
(Resp. Br. 7), and claim 1 does not recite “during programming.”
At the oral hearing, the parties disputed whether the Moshen figures
illustrate a single embodiment or multiple embodiments. Compare Tr. 22:3-
13 (Sidense: not different embodiments) with Tr. 31:9-19 (Kilopass:
different embodiments). Because Kilopass did not raise this issue in either
of its briefs, it is waived. See 37 C.F.R. § 41.73(e)(1) (“At the oral hearing,
each appellant . . . may only . . . present argument that has been relied upon
in the briefs” with an inapplicable exception.). We nevertheless conclude
that the Examiner correctly relied upon Figures 1, 2, and 9 because the
process illustrated in Figure 9 can incorporate the PLIDE
2
shown in Figures
1 and 2. See Mohsen col. 3, ll. 23-25; col. 7, ll. 63-66.
a channel region
Claim 1 recites a channel in part as follows: “first and second doped
semiconductor regions formed in said substrate adjacent said gate and in a
spaced apart relationship to define a channel region therebetween.”

2
PLIDE: programmable low impedance interconnect diode. See Moshen
col. 1, ll. 12-14.
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The Examiner finds that Moshen discloses this limitation in Figure
9(e): the first and second doped regions are elements 232 and the channel
region is element 218. RAN 8, citing col. 7, l. 63-col. 8, l. 51.
Kilopass contends the Examiner is incorrect because Moshen states
that a layer of photoresist 216 has been applied to the wafer as a mask “to
define the PLIDE region 218.” App. Br. 13, citing Moshen col. 8, ll. 6-7.
We are not persuaded by this argument because, as Sidense points out,
“[w]hether Moshen uses a mask or some other process to define channel
region 218 is not relevant. Instead, the inquiry based on the claim language
is whether, structurally, Moshen discloses two doped regions that are spaced
apart so as to define a channel region between them. . . Thus Appellant’s
process distinction cannot be given any weight.” Resp. Br. 8.
Kilopass also contends the Examiner is incorrect because, according
to Kilopass, the PLIDE is formed from p-type boron (App. Br. 9 n.5),
implants 232 are also p-type, and this forms one continuous p-type
conducting bottom electrode rather than providing doped regions that are
separated by a channel region. App. Br. 9. Therefore, according to
Kilopass, element 218 cannot be a channel because a channel is an area
where current flows between the source and drain and here, because
elements 218 and 232 are all p-type, “the current is not flowing between the
two areas.” Tr. 33:19-23.
Kilopass, however, provides no evidence in support of these
interpretations of Moshen. On the other hand, at the hearing, Kilopass twice
referred to element 218 as “channel 218.” See Tr. 7:19, 23.
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In the absence of evidence supporting Kilopass’s interpretation of
Moshen, we are not persuaded that the Examiner erred in correlating
Moshen’s element 218 to the channel recited in claim 1 and in claims 8, 19,
23, 28, and 34.
a programmed doped region formed in said substrate in said
channel region when said memory cell has been programmed

The Examiner finds that Moshen Figure 2 discloses a programmed
doped region 18 in the substrate 10 when the cell is programmed. RAN 8-9.
Kilopass contends instead that because Moshen’s melted plug 18 is formed
within bottom electrode 12, “Moshen does not teach a programmed doped
region in the substrate” 10. App. Br. 12.
We are not persuaded of Examiner error at least because Moshen
Figures 1 and 2 show bottom electrode 12 within substrate 10 and Kilopass
has not persuaded us why plug 18 cannot be considered also to be within
substrate 10. We also agree with the Examiner that “it cannot be said that
channel region 218 is separate from substrate 200 just because it has an
opposite conductivity to the substrate within which it is formed. To the
extent Moshen forms the programmed doped region in channel region 213
[sic 218] such programmed doped region is also formed in substrate 200
since channel region 213 [sic 218] is formed in substrate 200.” RAN 23-24.
We are not persuaded therefore that the Examiner erred in finding that
Moshen discloses the claimed programmed doped region formed in said
substrate in said channel region when said memory cell has been
programmed as recited in claim 1 and as also recited in claims 8, 19, 23, 28,
and 34.
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Accordingly, because we agree that the Examiner did not err in
finding that Moshen discloses the “channel region” limitation and
“programmed doped region” limitation, we conclude that the Examiner did
not err in rejecting claims 1, 8, 19, and 23 as anticipated by Moshen.
3

gate is laterally offset
Claim 3 recites “[t]he memory cell of claim 1 wherein said gate is
laterally offset from both said first and second doped semiconductor regions,
whereby said gate does not overlap with either of said first and second doped
semiconductor regions.”
The Examiner finds that Moshen Figures 9(d) and 9(e) show that gate
226 does not overlap the adjacent source/drain regions 232. RAN 9.
Kilopass acknowledges that there is a lateral separation between the gate and
the source and drain:
JUDGE TURNER: . . .In respect to Moshen, if anything, direct your
attention to Figure 9 of Moshen. . . And we look at the rightmost
region, the gate there. It looks like there’s a separation, at least
laterally, between that gate and the sourcing [sic] drain underneath it.
Isn’t there a separation there?

MR. NG: Yes, there is a separation.
Tr. 7:5-11.
Accordingly, we are not persuaded that the Examiner erred in finding
that Moshen discloses this limitation in claim 3 and in claims 10, 29, and 35

3
As explained below, we conclude that the Examiner erred in rejecting
claims 28 and 34 for other reasons.
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which are substantially the same as claim 3. We therefore conclude that the
Examiner did not err in rejecting claims 3 and 10 as anticipated by Moshen.
4

distance D that is sufficient to prevent directly short circuiting during
programming

Claim 5 recites “[t]he memory cell of claim 1 wherein said gate and
said second doped semiconductor region do not overlap and the second
doped semiconductor region is laterally separated from an edge of the gate
by a distance D that is sufficient to prevent directly short circuiting during
programming.” The Examiner finds a middle transistor in Figure 9(e)
includes gate 226 and a left doped region 232 that are laterally separated by
a distance “D” established by the thickness of the thermal oxide 230 and
mask 234 added prior to implantation of the doped regions 232. RAN 9,
citing Moshen col. 8, ll. 29-40. As shown above, Kilopass agrees there is a
separation.
Regarding the claimed preventing short circuiting during
programming, the Examiner finds that “Moshen does not disclose any
[short] circuiting during or after programing [sic]; thus the D must be
sufficient to prevent it.” RAN 9. Kilopass agrees “[t]here is no discussion
in Moshen that the gate and the doped semiconductor regions should be
separated by a distance that is sufficient to prevent a direct short circuit
during programming.” App. Br. 16.
Instead, Kilopass provides an interpretation of Moshen that Kilopass
does not support with evidence: “Electrically speaking, regions 232 and 218

4
As explained below, we conclude that the Examiner erred in rejecting
claims 29 and 35 for other reasons.
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short together and form a single electrode since all regions are of the same
conductivity type. Therefore, any punch through into the region 218 is
clearly short circuited into the doped semiconductor region 232.” App. Br.
16. Kilopass also contends that “[i]f a short circuit were to occur, the
memory cell would be inoperable.” Reb. Br. 5.
Kilopass’s arguments do not persuade us that the Examiner’s
interpretation of Moshen is erroneous. First, Kilopass does not present any
evidence that regions 232 and 218 short together and that any punch through
into region 218 is short circuited into regions 232. Second, Kilopass’s
assertion of a short circuit between elements 232 and 218 is undercut by its
additional assertion that if a short circuit were to occur, the memory cell
would be inoperable. Kilopass does not contend, or present evidence, that
the embodiment in Moshen’s Figure 9 is inoperable in part or in whole
because of such a short circuit.
Accordingly, we are not persuaded that the Examiner erred in
rejecting claim 5, or claims 6, 12, 13, 19, 22, 23, and 25-27 having similar
limitations, as anticipated by Moshen.
5

Claims 7, 14, 28, and 34 - floating
Claim 7 recites “The memory cell of claim 1 wherein said first doped
semiconductor region is floating.”
“Floating” is defined as “[t]he condition wherein a device or circuit is
not grounded and not tied to an established voltage supply.” McGraw-Hill
Electronics Dictionary, Sixth Edition 177 (1997).

5
Although claims 31-33 and 37-39 also have similar limitations, as
explained below, we conclude that the Examiner erred in rejecting those
claims for other reasons.
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At the oral hearing, Sidense agreed that in Figure 3 of the ‘757 Patent
you can clearly see that where it says the regions, for example,
308, are floating those are simply the regions that are not
contacted to whereas regions 306 are contacted to.

So, you know, interpreting the term “floating” in its broad sense
in view of what’s shown in Figure 3, the distinction between
the regions, the doped regions that are floating and those that
are not, is merely making contact to the particular regions,
based on what’s shown here.

Tr. 24:9-16.
The Examiner finds that Moshen elements 232 correlate to the
claimed first and second doped semiconductor regions (RAN 8) and that
Figures 5b, 6, 8a, and 8b and column 6, lines 17-49 of Moshen disclose “the
third terminal (i.e. first doped region) is floating.” RAN 10. Although the
Examiner identifies Moshen elements 232 in Figure 9 as the first and second
doped semiconductor regions (RAN 8), we cannot discern from the RAN
what in Figures 5b, 6, 8a, 8b, or 9(e) the Examiner considers to be “the third
terminal” or the “first” doped region. We also cannot discern from the RAN
how the Examiner concludes that Figures 5b, 6, 8a and 8b relate to Figure
9(e).
Kilopass first contends that Figures 5b and 6 do not mention a floating
first doped semiconductor region. App. Br. 14. Secondly, Kilopass
contends that
in Figure 9(e), the regions (232) on both sides of bottom
electrode 218 require external connections to the word line.
Specifically, both regions 232 have vias formed through the
glass passivation layer 236 and the vias are filled with metal
plugs 238. This means that the doped regions 232 are not and
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cannot be floating because all 232 regions are electrically
connected using the metal plugs 238.

App. Br. 14.
Sidense, like the Examiner, also does not explain the relationship
among these figures. Instead, Sidense first discusses Figures 5b and 6
together (Resp. Br. 10-11) and then discusses elements 232 and 218 of
Figure 9 separately (Resp. Br. 11) without explaining how Figures 5b and 6
relate to Figure 9.
In fact, Sidense asserts that “Figure 5B, Figure 6, and Figure 7 are
three different embodiments of the array that Moshen has described.” Tr.
24:23-25:2. Even assuming, therefore, that Figures 5b, 6, or 7 disclose an
embodiment with a floating element (which we do not find), neither the
Examiner nor Sidense have demonstrated that Figures 5b, 6, or 7 can be
combined with Figure 9 to support the stated anticipation rejection. For a
§ 102 anticipation rejection,
it is not enough that the prior art reference . . . includes
multiple, distinct teachings that the artisan might somehow
combine to achieve the claimed invention. See [In re] Arkley,
455 F.2d [586,] 587 (“[T]he [prior art] reference must clearly
and unequivocally disclose the claimed [invention] or direct
those skilled in the art to the [invention] with any need for
picking, choosing, and combining various disclosures not
directly related to each other by the teachings of the cited
reference.”

Net MoneyIN, Inc. v. Verisign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
We therefore agree with Kilopass that Figure 9(e) shows regions 232
having external connections to the wordline using vias that are filled with
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metal plugs 238 and are therefore not floating. We are also not persuaded
that any of the other Moshen figures disclose the floating recitation.
Accordingly, we are persuaded that the Examiner erred in concluding
that Moshen discloses the floating limitation in claims 7, 14, 28, and 34 and,
therefore, that the Examiner erred in rejecting claims 7, 14, and 28-39.
claims 17 and 18
Claims 17 and 18, dependent from independent claims 1 and 8,
respectively, each recite
the memory cell is configured to be programmed upon
application of a voltage difference between the gate and the
second doped semiconductor region that is greater than a
breakdown voltage of the gate dielectric and to be read by
application of a voltage difference between the gate and the
second doped semiconductor region that is less than the
breakdown voltage of the gate dielectric.

configured to be programmed upon application of a voltage difference
between the gate and the second doped semiconductor region

Citing Moshen column 5, lines 15-38 and column 7, lines 40-58, the
Examiner finds that Moshen discloses this limitation. RAN 11.
Specifically, Moshen discloses that “[t]he PLIDE element is programmed by
applying a voltage across the two electrodes 44 and 48.” Col. 5, ll. 16-17.
Kilopass’s various responses to the Examiner’s findings do not
persuade us that the Examiner has erred. Kilopass first refers to Moshen’s
element 48 as a gate and states that Moshen applies a voltage “between gate
48 and the electrode 44.” App. Br. 15. Kilopass then states that Moshen
applies a voltage “to both doped regions of 232 and bottom electrode of
218.” Id. Kilopass then states that Moshen applies a voltage between the
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gate and the bottom electrode 218. Reb. Br. 4. Trying to make sense of
Kilopass’s assertions, Sidense states that Kilopass
seems to be trying to draw the distinction that Moshen applies a
breakdown voltage across the gate and both the bottom
electrode 218 and the doped regions 232, while claim 17
requires that the breakdown voltage be applied across the gate
and only one doped region. However, claim 17 is not limited in
this manner. Given that [Kilopass] acknowledges that Moshen
applies the breakdown voltage across the gate the both doped
regions 232, then the claim limitation that the breakdown
voltage is applied across the gate and one doped region is
clearly satisfied.

Resp. Br. 12-13.
We agree with Sidense and we not persuaded, therefore, that the
Examiner erred in concluding that Moshen discloses this limitation.
configured to be . . . read by application of a voltage difference
between the gate and the second doped semiconductor region that is
less than the breakdown voltage of the gate dielectric

The Examiner finds that “it is implicit in the reference that [in] the
reading operation the voltage must be lower than the breakdown voltage of
the gate dielectric.” RAN 11. Kilopass argues that “[t]here is absolutely no
teaching in Moshen as to what voltages are applied in order to read the
PLIDE device.” App. Br. 15 (emphasis omitted). Although we agree with
Kilopass’s statement, we are persuaded by the Sidense’s explanation. At
pages 13-14 of its Respondent Brief, Sidense points to Moshen column 4,
lines 29-35 which explains that in order to program the cell, Moshen uses a
voltage above the breakdown voltage of the dielectric layer. Thus, explains
Sidense,
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to cause Moshen’s gate oxide to breakdown a voltage greater
than the gate oxide breakdown voltage needs to be applied
across the gate oxide. It necessarily follows that in reading
Moshen’s transistor, any voltage that is applied across
Moshen’s gate oxide must be lower than the gate oxide
breakdown voltage, otherwise the gate oxide would breakdown.

Resp. Br. 14. Kilopass does not respond to Sidense’s interpretation of the
claimed “read” limitation. See Reb. Br. 4-5.
Accordingly, we are not persuaded that the Examiner erred in finding
that Moshen discloses this limitation and in rejecting claims 17 and 18 as
anticipated by Moshen.
The Obviousness Rejections
claims 4, 11, 30, and 36
Dependent claim 4 recites “the gate dielectric of the transistor is
thicker proximal to the first and second doped semiconductor regions than at
said channel region.” The Examiner has rejected claim 4 as obvious over
Moshen in view of Bertin ‘410. Citing Figure 7 and column 5, lines 35-49
of Bertin ‘410, the Examiner finds that Bertin ‘410 teaches the gate (30)
dielectric (28) is thicker in the region proximal to the respective first and
second doped semiconductor regions (34). RAN 15. Thus, the Examiner
concludes, “the transistor of Moshen replaced by the MOSFET of Bertin
(‘410) – obvious for the reasons indicated in conjunction with Claim(s) 1
and 8 above – necessarily has the gate dielectric of the transistor thicker
proximal to the first and second doped semiconductor regions than at said
channel regions.” Id.
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Other than generally asserting that these claims are patentable over
Moshen in view of Bertin ‘410 (App. Br. 21)
6
, Kilopass presents no
argument specifically directed to these claims. In contrast, Kilopass presents
specific arguments directed to other specifically identified claims that have
been rejected over Moshen and Bertin ‘410 (See App. Br. 25) and presents
specific arguments directed to the rejection of these claims over a different
combination of references: Moshen in view of Bertin ‘120. See App. Br. 26.
In fact, Kilopass agrees that “Bertin ‘410 shows a MOSFET structure with
varying dielectric thicknesses. [Kilopass] agrees that there is prior art that
shows MOSFETs with varying dielectric thicknesses.” App. Br. 22.
Instead, Kilopass contends for various reasons that Bertin ‘410 cannot
be combined with Moshen because there is no incentive to combine them
and even if they were combined, the combination would be inoperable. See
App. Br. 22-24. We therefore review the Examiner’s conclusion that it
would have been obvious to combine Moshen and Bertin ‘410 and the
parties’ contentions regarding that conclusion.
The Examiner discusses the obviousness of the combination in
connection with independent claims 1 and 8. See RAN 15, relying upon
RAN 13-14. Specifically, the Examiner concludes that
it would have been obvious to one of ordinary skill in the art, at
the time of the invention to change the transistor in Moshen
with the MOSFET taught in Bertin ‘410 in order to (i) reduce
the dielectric rupture voltages required for programming (ii)
enable tailoring of the programming region of the transistor and

6
“Claims 1, 3-8, and 10-39 are patentable over Moshen in view of Bertin
(‘410).”
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(iii) to reduce the gate to drain/source overlap capacitance, as
taught by Bertin (‘410).

RAN 14.
Kilopass asserts, without supporting evidence, that “substitution of a
MOSFET of Bertin into Moshen would literally scramble all of the
base/emitter/collector connections so that the control connections would not
work.” App. Br. 22. But Sidense points out that “[t]he substitution would
be to replace the PLIDE antifuse structure of Moshen with the antifuse
structure of Bertin ‘410’s” and that Kilopass provides no evidentiary support
for its “scramble” argument. Resp. Br. 18-19.
Kilopass also contends that the Examiner combined the two
references without any showing as to what the motivation or incentive would
have been to make the combination and, without providing any supporting
evidence, contends that there are operational reasons why one of ordinary
skill in the art would not have made the combination. App. Br. 24-25.
These arguments are not persuasive because of the lack of supporting
evidence and because, as Sidense points out, the combination would replace
Moshen’s antifuse element with the antifuse structure of Bertin ‘410. We
agree with Sidense because the substitution of Bertin ‘410’s antifuse element
for Moshen’s antifuse element is nothing more than the substitution of
known elements operating according to their established functions. See KSR
Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007) (where “a patent claims
a structure already known in the prior art that is altered by the mere
substitution of one element for another known in the field, the combination
must do more than yield a predictable result.”)
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For the above reasons, we are not persuaded that the Examiner erred
in concluding that the limitation in (1) claim 4; and (2) claim 11 having
similar recitations are obvious over Moshen in view of Bertin ‘410.
Although claims 30 and 36 have similar recitations, we conclude that the
Examiner erred in rejecting those claims for the reasons explained above.
CONCLUSIONS
We conclude that the Examiner did not err in rejecting claims 1, 3-6,
8, 10-13, and 15-27. We conclude that the Examiner did err in rejecting
claims 7, 14, and 28-39 because Moshen does not disclose the “floating”
limitation in claims 7, 14, 28, and 34. Affirmance of the rejections of the
above referenced claims based on Moshen or based on Moshen and Bertin
‘410 renders it unnecessary to reach the propriety of the Examiner’s decision
to reject those claims on a different basis. In re Gleave, 560 F.3d 1331,
1338 (Fed. Cir. 2009).
DECISION
The rejection of claims 1, 3-6, 8, 10-13, and 15-27 is affirmed. The
rejection of claims 7, 14, and 28-39 is reversed.
AFFIRMED-IN-PART
In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this is decision becomes final and
appealable under 37 C.F.R. § 41.81, a party seeking judicial review must
timely serve notice on the Director of the United States Patent and
Trademark Office. See 37 C.F.R. §§ 90.1 and 1.983.

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Patent 6,777,757 B2

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PATENT OWNER:

PERKINS COIE LLP
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