Ex Parte 6,715,020 et al

Patent Trials and Appeals Board

Jan 11, 2013

95001472 - (S) (P.T.A.B. Jan. 11, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,472 10/20/2010 6,715,020 42940.27 4483
86497 7590 07/16/2013
Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
07/16/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

NVIDIA CORPORATION
Requester and Appellant

v.

RAMBUS INC.
Patent Owner and Respondent
____________

Appeal 2012-012567
Reexamination Control 95/001,472
Patent 6,715,020 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge

DECISION ON APPEAL
Appeal 2012-012567
Reexamination Control 95/001,472
Patent 6,715,020 B2

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The previously issued decision dated January 11, 2013 (“previous
decision”) is hereby vacated. The present Decision supersedes and replaces
the previous decision.
Third Party Requester and Appellant Nvidia Corporation appeals
under 35 U.S.C. §§ 134 and 315 the Examiner’s decision not to maintain
certain rejections of claims 1, 2, 5-7, 13-16, 38, 41, 42, 44, and 47-49 (see
below). Patent Owner appeals under 35 U.S.C. §§ 134 and 315 the
Examiner’s rejection of claims 1, 2, 5, 13, 38, 41, 44, and 47 (see below).

STATEMENT OF THE CASE
This proceeding arose from a request by Nvidia Corporation for an
inter partes reexamination of U.S. Patent 6,715,020 B2, titled “Synchronous
Integrated Circuit Device,” and issued to Michael Farmwald and Mark
Horowitz on March 30, 2004 (the ‘020 patent).
The ’020 patent describes a synchronous dynamic random access
memory device (Abstract).

Claim 1 reads as follows:
1. A controller device for controlling a synchronous dynamic
random access memory device, the controller device comprises:
first output driver circuitry to output block size information to the
memory device, wherein the block size information defines an amount of
data to be output by the memory device; and
input receiver circuitry to receive the amount of data output by the
memory device.

Requester appeals the Examiner’s refusal to adopt or maintain the
following proposed rejections:
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1) Claims 1, 2, 5-7, 13, 16, 38, 41, 42, 44, 47, and 49 under 35
U.S.C. § 103(a) as unpatentable over the combination of U.S. Patent No.
4,734,909 (“Bennett”) and Intel Corporation, Memory Components
Handbook, Chapter 1 and Chapter 3, Application Note AP-132, 1982/1985
(“iRAM”) (Right of Appeal Notice (RAN) 24-28) or the combination of
U.S. Patent No. 5,025,366 (“Baror”) and U.S. Patent No. 4,851,990
(“Johnson”) (RAN 29-30);
2) Claims 6, 7, and 42 under 35 U.S.C. § 103(a) as unpatentable
over Baror and iRAM (Action Closing Prosecution (ACP) 30-32); and
3) Claims 14-16, 48, and 49 under 35 U.S.C. § 103(a) as
unpatentable over Baror and either Japanese Patent No. 57-210495
(“Inagaki”) (RAN 41) or the combination of Inagaki and iRAM (RAN 41-
44).

Patent Owner appeals the Examiner’s rejection of claims 1, 2, 5, 13,
38, 41, 44, and 47 under 35 U.S.C. § 103(a) as unpatentable over the
combination of Baror and iRAM.

ANALYSIS

Patent Owner’s Appeal
Patent Owner argues that “neither Baror nor iRAM discloses or
suggests a controller device that outputs block size information to a
synchronous dynamic random access memory device as claimed” (PO App.
Br. 2).
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In particular, Patent Owner argues that Baror discloses that the
integrated cache unit of Baror “must be adequate to satisfy the data and
instruction needs of the high speed RISC processors that the integrated cache
unit supports” but that the “DRAM [of iRAM] cannot satisfy those
requirements” (PO App. Br. 5, citing Murphy Decl. ¶ 27 and Supp. Murphy
Decl. ¶¶ 5-8). However, even assuming to be correct Patent Owner’s
contention that “data and instruction needs” for RISC processors are “high,”
as the Examiner points out, “Baror is not limited to a specific memory and . .
. is not limited to using a RISC processing system” (RAN 22, citing Baror,
col. 1, ll. 45-49 and col. 2, ll. 1-2, 38-39). We disagree with Patent Owner
that one of ordinary skill in the art, given the disclosure of Baror as
“implement[ing] cache function in . . . [a] non-RISC environment” (col. 2, ll.
1-2), would have considered “data instruction needs of . . . [a] RISC
processor” to be a requirement.
In any event, “[t]he test for obviousness is not whether the features of
a secondary reference may be bodily incorporated into the structure of the
primary reference . . . Rather, the test is what the combined teachings of
those references would have suggested to those of ordinary skill in the art”
In re Keller, 642 F.2d 413, 425 (CCPA 1981). We are therefore not
persuaded by Patent Owner’s assertion that the memory device of iRAM
may not be bodily incorporated into the structure of Baror.
Patent Owner also argues that it would not have been obvious to one
of ordinary skill in the art to have combined the teachings of Baror with that
of iRAM because, according to Patent Owner, the integrated cache unit of
Baror “is capable of operating at frequencies in excess of 25 megahertz” but
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that that DRAMs of iRAM “could not provide such high speed operation”
(PO App. Br. 4). As the Examiner points out, however, Baror discloses the
cache unit of Baror “capable of operating at frequencies in excess of 25
megahertz” (col. 2, ll. 17-18) with use of a “RISC processor and two ICUs”
(col. 2, ll. 24-25) but does not disclose any specific requirements as to
operating frequencies when functioning in a “non-RISC environment” (col.
2, ll. 1-2). Even assuming Patent Owner’s contention to be correct that
“operating at frequencies in excess of 25 megahertz” is required in an RISC
environment and that the DRAM of iRAM is incapable of operating at “such
high speed operation,” Patent Owner has not demonstrated that operating
frequencies “in excess of 25 megahertz” is required in a non-RISC
environment (a non-RISC environment being another embodiment of Baror).
In any event, as also pointed out by the Examiner, “Baror teaches that
25 megahertz is merely a preferred embodiment” (RAN 21) but does not
require a specific operating frequency.
Patent Owner argues that “DRAMs [of iRAM] provide ‘moderate
speeds,’ and are not suitable for high speed caches such as the integrated
cache units of Baror” because the “integrated cache unit [of Baror] . . .
requires higher performance than the ‘moderate speed’ of DRAMS [of
iRAM] and cannot be saddled with the additional timing penalties resulting
from the need to refresh a DRAM array” (PO App. Br. 3). However, as
above and as indicated by the Examiner, Baror does not disclose specific
requirements pertaining to the cache units. While Patent Owner argues that
the cache units of Baror requires “higher performance,” Patent Owner does
not sufficiently demonstrate that the DRAM as disclosed by iRAM is
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incapable of providing speeds that are sufficiently “high” for either one of
Baror’s “RISC” or “non-RISC” environments (see, e.g., col. 2, l. 2).
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined the teachings of Baror with that of
iRAM because, according to the Patent Owner, the DRAM of iRAM
“requires refreshing” and, “if included in the integrated cache unit” of Baror,
would also require one of ordinary skill in the art to add “refresh control
circuitry.” This, according to Patent Owner “would have prevented the
integrated cache unit [of Baror] from responding to requests . . . until a
refresh operation was complete” and that would have resulted in a “non-
responsive integrated cache unit [that] would have starved the processor and
force it to enter a wait state” (PO App. Br. 6, citing Murphy Decl. ¶ 28 and
Supp. Murphy Decl. ¶¶ 9-12).
We disagree with Patent Owner for at least the reasons set forth by the
Examiner and set forth above. Even assuming that “refresh control
circuitry” would have been necessary in the Baror system as Patent Owner
asserts, Patent Owner does not contend or demonstrate that adding such
circuitry would have been “uniquely challenging or difficult for one of
ordinary skill in the art.” See Leapfrog Enters., Inc. v. Fisher-Price, Inc.,
485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418).
While Patent Owner assumes that adding “refresh control circuitry” to
the Baror system would have been necessary and that such circuitry would
have “starved the processor and forced it to enter a wait state,” Patent Owner
does not demonstrate that it would not have been obvious to one of ordinary
skill in the art to have combined the teachings of Baror and iRAM,
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particularly in view of the fact that a DRAM provides “high capacity,
moderate speeds and low power consumption” (RAN 32, citing iRAM, p. 1-
1), which Patent Owner does not appear to refute.
Patent owner also argues that “Baror does not disclose . . . block size
information provided to a synchronous dynamic random access memory
device” (PO App .Br. 11). However, as the Examiner points out, Baror
discloses, for example, “OPT0-OPT2, Option Control” that “are used for
specifying the data length” (col. 9, ll. 20-21). We agree with the Examiner
that Baror discloses “block size information” as recited in claim 1, for
example, for at least the reasons set forth by the Examiner (see, e.g., ACP
26-30).
While Patent Owner argues that Baror discloses a “word of data” but
that “a single word is not considered a block of data” (PO App. Br. 12, citing
Murphy Decl. at ¶ 32), Patent Owner does not demonstrate that one of
ordinary skill in the art would have considered a particular size “word” to be
different from a particular size “block of data.” Even assuming that Baror
discloses a “word of data” as Patent Owner contends, Patent Owner does not
indicate an explicit definition of “block size” as excluding a “word of data.”
In the absence of such a definition, we agree with the Examiner that one of
ordinary skill in the art would have understood that the amount or size of
data (or block size) would have encompassed a single word of data. We also
agree with United States District Judge Ronald M. Whyte that specifying
“one data word” in another prior art reference satisfies the claim. ” (Order
Granting in Part and Denying in Part Rambus’s Motion to Strike; Denying
Motion for summary Judgment No. 1 of Invalidity; and Striking Motion for
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summary Judgment No. 2 of Invalidity – C-05-00334 RMW issued
December 15, 2008, 3PR App. Br., Exhibit 10, p. 32).
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined the teachings of Baror and iRAM
because, according to Patent Owner, “there was a need to develop
technology that improved the speed and efficiency of data transfer” (PO
App. Br. 13). However, as the Examiner indicates, even assuming that there
was a need to improve speed and efficiency of data transfer, Patent Owner
has not demonstrated that others tried and failed to improve speed and
efficiency of data transfer. Norgren Inc. v. Int’l Trade Com’n, 699 F.3d
1317, 1327 (Fed. Cir. 2012) (finding insufficient evidence to show non-
obviousness with long-felt need if no showing that others tried and failed).
Instead, Patent Owner merely states that “Dr. Michael Farmwald, one of the
inventors, . . . recognized that the need for improved memory performance
would be . . . acute” (PO App. Br. 13) and that “Dr. Farmwald and Dr. Mark
Horowitz, the other named inventor” utilized “synchronous memory
devices.” (id.).
Patent Owner also argues that “the inventions claimed in the claims
were met with skepticism” (PO App. Br. 14) and that skepticism was
observed in response to the notion that “Drs. Farmwald and Horowitz would
be able to achieve a 500 megabit per second DRAM data rate” (id.). Even
assuming that the inventors met with skepticism over attaining “a 500
megabit per second DRAM data rate,” Patent Owner does not demonstrate
or assert that Dr. Farmwald or Horowitz met with any “skepticism” over
“the inventions claimed in the claims” – e.g., a controller device outputting
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Patent 6,715,020 B2

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block size information defining an amount of data to a memory device and
receiving the amount of data output by the memory device.
Patent Owner also argues that “synchronous memory devices and the
controllers that control them have had great commercial success” (PO App.
Br. 15) but, as indicated by the Examiner, Patent Owner does not provide
specific evidence of commercial success or the required nexus between any
alleged commercial success and the claimed invention. “Evidence of
commercial success, or other secondary considerations, is only significant if
there is a nexus between the claimed invention and the commercial success.”
Ormco Corp. v. Align Tech., Inc., 463 F.3d 1299, 1311-12 (Fed. Cir. 2006).
Patent Owner argues that “Dr. Horowitz has been recognized . . . for
his work in the semiconductor memory field” (PO App. Br. 15) including
“pioneering contributions to design of high-performance digital integrated
circuits and systems” (id.). Even assuming Patent Owner’s contention to be
correct that Dr. Horowitz provided “pioneering contributions to design” of
circuits and “resolv[ed] the memory bottleneck problem” (id.), Patent Owner
has not indicated that Dr. Horowitz was “recognized” for work pertaining to
the claimed invention – e.g., a controller device outputting block size
information defining an amount of data to a memory device and receiving
the amount of data output by the memory device.
We are therefore not persuaded by Patent Owner’s arguments.

Requester’s Appeal
Appeal 2012-012567
Reexamination Control 95/001,472
Patent 6,715,020 B2

10
Requester “withdraws its appeal to the Board, including all of its
appeal briefs and supporting papers”
1
Hence, Appellant does not appear to
dispute the Examiner’s refusal to adopt or maintain the proposed rejections
of claims 1, 2, 5-7, 13, 16, 38, 41, 42, 44, 47, and 49 under 35 U.S.C. §
103(a) as unpatentable over the combination of Bennett and iRAM or the
combination of Baror and Johnson; claims 6, 7, and 42 under 35 U.S.C. §
103(a) as unpatentable over Baror and iRAM; and claims 14-16, 48, and 49
under 35 U.S.C. § 103(a) as unpatentable over Baror and either Inagaki or
the combination of Inagaki and iRAM.

DECISION
We affirm the Examiner’s decision not to maintain the rejection of
claims 1, 2, 5-7, 13, 16, 38, 41, 42, 44, 47, and 49 under 35 U.S.C. § 103(a)
as unpatentable over the combination of Bennett and iRAM (RAN 24-28) or
the combination of Baror and Johnson; claims 6, 7, and 42 under 35 U.S.C. §
103(a) as unpatentable over Baror and iRAM; and claims 14-16, 48, and 49
under 35 U.S.C. § 103(a) as unpatentable over Baror and either Inagaki or
the combination of Inagaki and iRAM.
We affirm the Examiner’s rejection of claims 1, 2, 5, 13, 38, 41, 44,
and 47 under 35 U.S.C. § 103(a) as unpatentable over the combination of
Baror and iRAM.

1
Notice of withdrawal of Third-Party Requester’s Appeal and Other Papers,
filed February 17, 2012, p. 1.
Appeal 2012-012567
Reexamination Control 95/001,472
Patent 6,715,020 B2

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Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED

cu

PATENT OWNER:

PAUL M. ANDERSON, PLLC
P.O. BOX 160006
AUSTIN, TX 78716

THIRD PARTY REQUESTER:

HAYNES AND BOONE, LLP
IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219