Corning Optical Communications Wireless LtdDownload PDFPatent Trials and Appeals BoardMar 8, 20212019004368 (P.T.A.B. Mar. 8, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/049,663 02/22/2016 Daniel Dadoun HI13-109 1611 21495 7590 03/08/2021 CORNING INCORPORATED INTELLECTUAL PROPERTY DEPARTMENT, SP-TI-3-1 CORNING, NY 14831 EXAMINER SCHEIBEL, ROBERT C ART UNIT PAPER NUMBER 2467 NOTIFICATION DATE DELIVERY MODE 03/08/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): usdocket@corning.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte DANIEL DADOUN and GUY LUPESCU ____________ Appeal 2019-004368 Application 15/049,663 Technology Center 2400 ____________ Before JUSTIN BUSCH, CATHERINE SHIANG, and JASON J. CHUNG, Administrative Patent Judges. SHIANG, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1–24, which are all the claims pending and rejected in the application.2 We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 We use “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies Corning Optical Communications Wireless Ltd. (formerly “Corning MobileAccess Ltd.”), as the real party in interest. Appeal Br. 2. 2 The Examiner’s objection to claim 24 (Final Act. 5) is not before us. Appeal 2019-004368 Application 15/049,663 2 STATEMENT OF THE CASE Introduction The present invention relates to “time-division duplexed (TDD) communications equipment configured to communicate TDD communications signals over a common communications medium and more particularly to detecting TDD frame configurations in TDD communications signals which may be used in synchronizing downlink and uplink communications between TDD communications equipment.” Spec. ¶ 2 (emphases omitted). Claims 1, 5, 10, 11, and 23 are exemplary: 1. A time-division duplexed (TDD) communications unit, comprising: a TDD communications signal interface configured to receive a downlink TDD communications signal over a communications medium; an uplink transmitter circuit coupled to the TDD communications signal interface, the uplink transmitter circuit configured to transmit an uplink TDD communications signal over the communications medium during at least one uplink frame period of a TDD frame based on a received uplink transmission control signal; a downlink receiver circuit coupled to the TDD communications signal interface, the downlink receiver circuit configured to be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal; and a controller configured to: detect an uplink/downlink TDD frame configuration of the TDD frame; determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration; generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame; and generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame. Appeal 2019-004368 Application 15/049,663 3 5. The TDD communications unit of claim 1, wherein the downlink reception control signal is comprised of the uplink transmission control signal. 10. The TDD communications unit of claim 7, wherein the controller is configured to create a TDD frame timing pattern from the detected uplink/downlink TDD frame configuration and the detected at least one transition in the TDD frame. 11. The TDD communications unit of claim 10, wherein the controller is further configured to synchronize the TDD frame timing pattern with the TDD frame, to determine the at least one uplink frame period in the TDD frame. 23. The method of claim 22, further comprising creating a TDD frame timing pattern from the detected uplink/downlink TDD frame configuration and the detected at least one transition in the TDD frame, wherein determining the at least one uplink frame period in the TDD frame further comprises synchronizing the TDD frame timing pattern with the TDD frame. Reference and Rejections3 Claim(s) Rejected 35 U.S.C. § References 5 112(b) 1–24 102 Stratford (US 2010/0041341 Al; published Feb. 18, 2010) 3 Throughout this opinion, we refer to the (1) Final Office Action dated Feb. 9, 2018 (“Final Act.”); (2) Appeal Brief dated Oct. 1, 2018 (“Appeal Br.”); (3) Examiner’s Answer dated Nov. 27, 2018 (“Ans.”); and (4) Reply Brief dated Jan. 25, 2019 (“Reply Br.”). Appeal 2019-004368 Application 15/049,663 4 ANALYSIS 35 U.S.C. § 112(b) The Examiner concludes claim 5 is indefinite with respect to the claim limitation “the downlink reception control signal is comprised of the uplink transmission control signal.” See Final Act. 6. The Examiner concludes: If the uplink and downlink signals are identical, the different meaning conveyed by each signal would not be apparent to the receiving device. That is, if a receiver interprets a first signal as an uplink signal, it is not clear how the receiver would subsequently interpret reception of the exact same (uplink) as a downlink signal. Perhaps the signals are transmitted using the same path, but are encoded differently. However, this is not what Appellant has claimed. Ans. 7 (emphases omitted). Appellant argues there is nothing unclear about this claim. In one embodiment, the “downlink reception control signal is comprised of the uplink transmission control signal.” This non-limiting embodiment is discussed in at least paragraph 0041 of the Specification, which reads in part: “The downlink reception control signal 50 may be the same signal as the uplink transmission control signal 54, as opposed to being different signals.” In light of the Specification, claim 5 is not indefinite. Appeal Br. 12. We agree with Appellant. “The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.” 35 U.S.C. § 112(b). We apply the indefiniteness test approved by In re Packard, 751 F.3d 1307 (Fed. Cir. 2014) (per curiam): “[a] claim is indefinite when it contains words or phrases whose meaning is unclear,” and “claims are required to be Appeal 2019-004368 Application 15/049,663 5 cast in clear–as opposed to ambiguous, vague, indefinite–terms.” See Packard, 751 F.3d at 1310, 1313; Ex parte McAward, Appeal No. 2015- 006416, 2017 WL 3669566, at *4–6 (PTAB Aug. 25, 2017) (precedential) (explaining that due to different approaches to indefiniteness before the PTAB and the courts, the PTAB continues to follow Packard after the Supreme Court’s Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898 (2014) decision). [W]hen the USPTO has initially issued a well-grounded rejection that identifies ways in which language in a claim is ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention, and thereafter the applicant fails to provide a satisfactory response, the USPTO can properly reject the claim as failing to meet the statutory requirements of § 112(b). Packard, 751 F.3d at 1311. Claim 5 recites “The TDD communications unit of claim 1, wherein the downlink reception control signal is comprised of the uplink transmission control signal” (emphasis added). The Specification further explains the disputed term as follows: The downlink reception control signal 50 may be the same signal as the uplink transmission control signal 54, as opposed to being different signals. For example, an inverter gate may be included between the downlink reception control signal 50 and the downlink receiver circuit 48 in the central unit 14, so that the downlink reception control signal 50 and the uplink transmission control signal 54 have opposite signal levels indicating different states for activation and deactivation. Alternatively, the downlink receiver circuit 48 or the uplink transmitter circuit 52 in the central unit 14 may be configured to be activated on an opposite signal level from the uplink transmitter circuit 52 or the downlink receiver circuit 48, respectively. Appeal 2019-004368 Application 15/049,663 6 Spec. ¶ 41 (emphasis added). Therefore, one skilled in the art would understand the meaning of the limitation “the downlink reception control signal is comprised of the uplink transmission control signal.” Contrary to the Examiner’s determination that “if a receiver interprets a first signal as an uplink signal, it is not clear how the receiver would subsequently interpret reception of the exact same (uplink) as a downlink signal” (Ans. 7), the Specification explains that the uplink and downlink circuits “may be configured to be activated on an opposite signal level” from the other circuit (Spec. ¶ 41). In short, the Examiner has not shown the meaning of the limitation is unclear to one skilled in the art. See Packard, 751 F.3d at 1310. Because the Examiner has not provided sufficient basis for the rejection, we reverse the Examiner’s rejection of claim 5 under 35 U.S.C. § 112(b). Anticipation On this record, the Examiner did not err in rejecting claim 1. We have reviewed and considered Appellant’s arguments, but such arguments are unpersuasive. To the extent consistent with our analysis below, we adopt the Examiner’s findings and conclusions in (i) the action from which this appeal is taken and (ii) the Answer.4 4 To the extent Appellant advances new arguments in the Reply Brief without showing good cause, Appellant has waived such arguments. See 37 C.F.R. § 41.41(b)(2). Appeal 2019-004368 Application 15/049,663 7 I Appellant contends Stratford does not disclose an uplink transmitter circuit coupled to the TDD communications signal interface, the uplink transmitter circuit configured to transmit an uplink TDD communications signal over the communications medium during at least one uplink frame period of a TDD frame based on a received uplink transmission control signal; a downlink receiver circuit coupled to the TDD communications signal interface, the downlink receiver circuit configured to be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal; and a controller configured to: detect an uplink/downlink TDD frame configuration of the TDD frame; determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration; generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame; and generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame, as recited in independent claim 1 (emphases added). See Appeal Br. 13–14; Reply Br. 4–8. In particular, Appellant argues the Examiner’s Answer states that “Stratford clearly discloses two circuits as well as two signals (transmitted on the same line).” Appellant respectfully disagrees. As an initial point, there is nothing in the annotated figure that shows that two signals are transmitted on the same line. In addition, Appellant . . . submits that Stratford does not disclose generating two Appeal 2019-004368 Application 15/049,663 8 control signals and does not disclose two different circuits being controlled by these two control signals. Reply Br. 4–5 (emphases omitted).5 Stratford . . . fails to disclose a “controller” that generates two signals. In claim 1, the controller generates two control signals, an “uplink transmission control signal” and a “downlink reception control signal,” which are respectively used to control two circuits – an “uplink transmitter circuit” and a “downlink receiver circuit.” . . . the Examiner’s Answer equates “microprocessor 314” in Stratford to the claimed “controller” and refers to a line between the “microprocessor 314” and the “switch 312” as a “control line for sending signals to control uplink/downlink mode.” Appellant . . . submits that simply switching between uplink and downlink mode, as alleged by the Patent Office and as disclosed in paragraph 0042 of Stratford, is not equivalent to what is being claimed in claim 1 – a controller that is configured to “detect an uplink/downlink TDD frame configuration of the TDD frame,” “determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration,” “generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame,” and “generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame.” . . . . In this manner, the “controller” of claim 1 generates two control signals, an “uplink transmission control signal” and a “downlink reception control signal,” which are respectively used to control two circuits – an “uplink transmitter circuit” and a “downlink receiver circuit.” The system in Stratford operates in a different manner. First, there is no mention in Stratford that two control signals are sent from the “microprocessor 314” to control two different circuits. Instead, in Stratford, a “switch 312” “switches circuit 300 between uplink mode and downlink mode by coupling RF duplex port 303 to either downlink port 5 Because the Examiner clarifies mappings in the Answer, Appellant has good cause to raise arguments in response to the clarification. Appeal 2019-004368 Application 15/049,663 9 304 (to receive signals from the communication medium coupled to RF duplex port 303) or uplink port 306 (to output signals to the communication medium coupled to RF duplex port 303).” Stratford, ¶ 0042. The downlink subframes are sampled and processed to create an “average” frame, which are summed and all samples above a threshold are integrated to form an integrated power curve. Stratford[] ¶¶ 0044-0049; see Figure 4, steps 402-408. The end of the downlink subframe is determined from the integrated power curve. Stratford, Figure 4, step 410. The “microprocessor 314” in Stratford “uses the information obtained in step 410 to set switch 312 to uplink mode ( coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204.” Stratford, ¶ 0054. So in Stratford, only a single signal is sent from the “microprocessor 314” to control a single device – the “switch 312” – to switch from downlink mode to uplink mode. Since the “switch 312” is switching the mode, there is no need to have the “microprocessor 314” in Stratford generate two control signals, an “uplink transmission control signal” and a “downlink reception control signal,” which are respectively used to control two circuits – an “uplink transmitter circuit” and a “downlink receiver circuit,” as is done in the claimed “TDD communications unit” of claim 1. . . . . Moreover, it is noteworthy that Stratford works by sending one signal from the “microprocessor 314” to the “switch 312.” As noted above, since the “switch 312” is switching the mode, there is no need to have the “microprocessor 314” in Stratford generate two control signals. In contrast, claim 1 recites that the “controller” generates two control signals, an “uplink transmission control signal” and a “downlink reception control signal,” which are respectively used to control two circuit – an “uplink transmitter circuit’’ and a “downlink receiver circuit.” Stratford does not teach this configuration as arranged in claim 1. Claim 1 is thus not anticipated by Stratford. Reply Br. 6–8 (emphases omitted). Appeal 2019-004368 Application 15/049,663 10 Appellant has not persuaded us of error. Turning to claim construction, it is well established that during examination, claims are given their broadest reasonable interpretation consistent with the specification, but without importing limitations from the specification. See In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004); SuperGuide Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004). In this case, claim 1 recites both a “downlink reception control signal” and an “uplink transmission control signal.” Claim 5, which depends from claim 1, recites: “The TDD communications unit of claim 1, wherein the downlink reception control signal is comprised of the uplink transmission control signal” (emphasis added). The Specification further explains the claimed “downlink reception control signal” and “uplink transmission control signal” may be the same signal: The downlink reception control signal 50 may be the same signal as the uplink transmission control signal 54, as opposed to being different signals. For example, an inverter gate may be included between the downlink reception control signal 50 and the downlink receiver circuit 48 in the central unit 14, so that the downlink reception control signal 50 and the uplink transmission control signal 54 have opposite signal levels indicating different states for activation and deactivation. Alternatively, the downlink receiver circuit 48 or the uplink transmitter circuit 52 in the central unit 14 may be configured to be activated on an opposite signal level from the uplink transmitter circuit 52 or the downlink receiver circuit 48, respectively. Spec. ¶ 41 (emphasis added). Therefore, interpreting claim 1 in light of claim 5 and the Specification, one skilled in the art would understand the broadest Appeal 2019-004368 Application 15/049,663 11 reasonable interpretation of claim 1 encompasses the claim construction that “the downlink reception control signal” and “the uplink transmission control signal” are the same signal. As a result, Appellant’s arguments that Stratford does not teach two different signals (Appeal Br. 13–14; Reply Br. 4–8) are unpersuasive. Further, Appellant acknowledges that “Stratford works by sending one signal from the ‘microprocessor 314’ to the ‘switch 312.’” Reply Br. 8 (emphasis omitted). Therefore, the acknowledged Stratford’s signal teaches both the “downlink reception control signal” and “uplink transmission control signal,” as required by claim 1. As a result, Appellant has not shown the Examiner erred in finding Stratford discloses an uplink transmitter circuit coupled to the TDD communications signal interface, the uplink transmitter circuit configured to transmit an uplink TDD communications signal over the communications medium during at least one uplink frame period of a TDD frame based on a received uplink transmission control signal; a downlink receiver circuit coupled to the TDD communications signal interface, the downlink receiver circuit configured to be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal; and a controller configured to: detect an uplink/downlink TDD frame configuration of the TDD frame; determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration; generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame; and Appeal 2019-004368 Application 15/049,663 12 generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame, as required by claim 1 (emphases added). II Appellant contends Stratford does not disclose a controller configured to: detect an uplink/downlink TDD frame configuration of the TDD frame; determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration; generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame; and generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame, as recited in independent claim 1 (emphases added). See Reply Br. 8. In particular, Appellant argues in Stratford, there is no mention that the “microprocessor 314” is configured to “detect an uplink/downlink TDD frame configuration of the TDD frame,” “determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration,” “generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame,” and “generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame,” as recited in claim 1. Instead, Stratford only discloses that the “microprocessor 314” “uses the information obtained in step 410 to set switch 312 to uplink mode (coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204.” Stratford, ¶ 0054. The information obtained in step 410 is all based on the processing Appeal 2019-004368 Application 15/049,663 13 of downlink subframes. Stratford, ¶¶ 0044-0049; see also Figure 4. Stratford does not mention generating any control signal based on a controller being configured to “detect an uplink/downlink TDD frame configuration of the TDD frame,” “determine at least one uplink frame period in the TDD frame based on the detected uplink/downlink TDD frame configuration,” “generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame,” and “generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame,” as recited in claim 1. Reply Br. 7–8. Appellant has not persuaded us of error. Stratford describes “[a]t block 410, the end of downlink subframe 202 is determined by microprocessor 314 from the integrated power curve.” Stratford ¶ 50. Further, [a]t block 412, microprocessor 314 uses the information obtained in step 410 to set switch 312 to uplink mode coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204. Once microprocessor 314 determines the length of downlink subframe 202 and/or the duty cycle of frame 200, this information is used to set switch 312 to uplink mode at the end of downlink subframe 202. Stratford ¶ 54 (emphases added); see also Stratford, Fig. 3 (below). Appeal 2019-004368 Application 15/049,663 14 Because Stratford discloses “microprocessor 314 uses the information obtained in step 410 to set switch 312 to uplink mode (coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204” and “microprocessor 314 determin[ing] . . . the duty cycle of frame 200” (Stratford ¶ 54), Stratford discloses “a controller configured to . . . determine at least one uplink frame period,” as required by claim 1 (emphasis added). In fact, Appellant acknowledges “‘microprocessor 314’ in Stratford ‘uses the information obtained in step 410 to set switch 312 to uplink mode (coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204’” Reply Br. 8 (emphasis added) (quoting Stratford ¶ 54). Appeal 2019-004368 Application 15/049,663 15 Further, Stratford discloses “[o]nce microprocessor 314 determines the length of downlink subframe 202 and/or the duty cycle of frame 200, this information is used to set switch 312 to uplink mode at the end of downlink subframe 202.” Stratford ¶ 54 (emphases added). In addition, “Switch 301 switches circuit 300 between uplink mode and downlink mode by coupling RF duplex port 303 to either downlink port 304 (to receive signals from the communication medium coupled to RF duplex port 303) or uplink port 306 (to output signals to the communication medium coupled to RF duplex port 303).” Stratford ¶ 42; see also Stratford Fig. 3 (showing the connection between microprocessor 314 and switch 312). Therefore, Stratford discloses a controller configured to: . . . generate the uplink transmission control signal based on the determined at least one uplink frame period in the TDD frame; and generate the downlink reception control signal based on the determined at least one uplink frame period in the TDD frame, as recited in independent claim 1 (emphases added). III Appellant contends Stratford does not disclose “a downlink receiver circuit coupled to the TDD communications signal interface, the downlink receiver circuit configured to be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal,” as recited in independent claim 1 (emphases added). See Appeal Br. 14; Reply Br. 5–6. In particular, Appellant argues: Appeal 2019-004368 Application 15/049,663 16 The Patent Office now, for the first time, seemingly takes the position that Stratford does disclose two “separate downlink and uplink circuits.” . . . . the Examiner is equating element 308 in Stratford to the claimed “downlink receiver circuit,” . . . . Element 308 in Stratford is a “variable resistor” that “controls the power of downlink signals output from downlink port 304.” Stratford, ¶ 0041. The “variable resistor 308” in Stratford is not “a downlink receiver circuit coupled to the TDD communications signal interface” and “configured be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal,” as recited in claim 1. . . . . The “variable resistor 308” in Stratford is not equivalent to the claimed “downlink receiver circuit.” Notably, there is no mention that the “variable resistor 308” in Stratford is “configured to be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal,” as recited in claim 1. . . . . There is no control signal sent from the “microprocessor 314” of Stratford (equated to the claimed “controller” of claim 1) to the “variable resistor 308.” There is no mention that the “variable resistor 308” in Stratford is deactivated “based on a received downlink reception control signal.” Instead, the “switch 312” simply couples the “RF duplex port 303 to either downlink port 304 . . . or uplink port 306.” Stratford[] ¶ 0042. The “variable resistor 308” in Stratford is never “deactivated to not sample the downlink TDD communications signal during the at least one uplink frame period of the TDD frame,” as recited in claim 1. Accordingly, the “variable resistor 308” in Stratford cannot be the claimed “downlink receiver circuit.” Claim 1 is thus not anticipated by Stratford for at least this reason. Reply Br. 4–6 (emphases omitted). Appellant’s arguments are unpersuasive because they are not directed to the Examiner’s specific findings. We understand the Examiner cites Appeal 2019-004368 Application 15/049,663 17 Stratford’s downlink circuit, which includes, but is not limited to, the variable resistor 308, for teaching the claimed “downlink receiver circuit.” See Ans. 6. Further, Stratford’s downlink circuit is “configured to be deactivated to not sample the downlink TDD communications signal during at least one uplink frame period of the TDD frame based on a received downlink reception control signal,” as required by claim 1, because the downlink circuit is disconnected from the switch—i.e., deactivated—when the control signal causes switch 312 to connect to—i.e., activate—the uplink circuit. See Stratford ¶ 42 (“Switch 301 switches circuit 300 between uplink mode and downlink mode by coupling RF duplex port 303 to either downlink port 304 (to receive signals from the communication medium coupled to RF duplex port 303) or uplink port 306 (to output signals to the communication medium coupled to RF duplex port 303).”); Stratford ¶ 54 (“At block 412, microprocessor 314 uses the information obtained in step 410 to set switch 312 to uplink mode (coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204. Once microprocessor 314 determines the length of downlink subframe 202 and/or the duty cycle of frame 200, this information is used to set switch 312 to uplink mode at the end of downlink subframe 202.”). IV Appellant contends Stratford does not disclose “an uplink transmitter circuit coupled to the TDD communications signal interface, the uplink transmitter circuit configured to transmit an uplink TDD communications signal over the communications medium during at least one uplink frame period of a TDD frame based on a received uplink transmission control Appeal 2019-004368 Application 15/049,663 18 signal,” as recited in independent claim 1 (emphases added). See Reply Br. 6. In particular, Appellant argues element 310 in Stratford is not equivalent to the claimed “uplink transmitter circuit” of claim 1. In claim 1, the “uplink transmitter circuit” is “coupled to the TDD communications signal interface” and “configured to transmit an uplink TDD communications signal over the communications medium during at least one uplink frame period of a TDD frame based on a received uplink transmission control signal.” The only sentence that mentions element 310 in Stratford is in paragraph 0041 and states: “On the uplink side, an amplifier 310 amplifies signals received from wireless terminals 112 for further processing and outputting to base station 102.” The “amplifier 310” in Stratford is not equivalent to the claimed “uplink transmitter circuit.” Notably, there is no mention that the “amplifier 310” in Stratford is “configured to transmit an uplink TDD communications signal during at least one uplink frame period of the TDD frame based on a received uplink transmission control signal,” as recited in claim 1. . . . . There is no control signal sent from the “microprocessor 314” of Stratford (equated to the claimed “controller” of claim 1) to the “amplifier 310.” Instead, the “switch 312” simply couples the “RF duplex port 303 to either downlink port 304 . . . or uplink port 306.” Stratford, ¶ 0042. The “amplifier 310” in Stratford does not take action “based on a received uplink transmission control signal,” as recited in claim 1. . . . . Accordingly, the “amplifier 310” in Stratford cannot be the claimed “uplink transmitter circuit.” Claim 1 is thus not anticipated by Stratford for at least this additional reason. Reply Br. 6 (emphases omitted). Appellant’s arguments are unpersuasive because they are not directed to the Examiner’s specific findings. We understand the Examiner cites Stratford’s uplink circuit, which includes, but is not limited to, the amplifier 310, for teaching the claimed “uplink receiver circuit.” See Ans. 6. Further, Appeal 2019-004368 Application 15/049,663 19 Stratford’s uplink circuit is “configured to transmit an uplink TDD communications signal over the communications medium during at least one uplink frame period of a TDD frame based on a received uplink transmission control signal,” as recited in independent claim 1 (emphases added). See Stratford ¶ 42 (“Switch 301 switches circuit 300 between uplink mode and downlink mode by coupling RF duplex port 303 to either downlink port 304 (to receive signals from the communication medium coupled to RF duplex port 303) or uplink port 306 (to output signals to the communication medium coupled to RF duplex port 303).”); Stratford ¶ 54 (“At block 412, microprocessor 314 uses the information obtained in step 410 to set switch 312 to uplink mode (coupling signals from uplink port 306 to RF duplex port 303) for subsequent uplink subframes 204. Once microprocessor 314 determines the length of downlink subframe 202 and/or the duty cycle of frame 200, this information is used to set switch 312 to uplink mode at the end of downlink subframe 202.”).6 Because Appellant has not persuaded us the Examiner erred, we sustain the Examiner’s rejection of independent claim 1, and independent claims 18 and 24 for similar reasons. We also sustain the Examiner’s rejection of corresponding dependent claims 2–4, 6–9, 12–17, and 19–22, as Appellant does not advance separate substantive arguments about those claims. See 37 C.F.R. § 41.37(c)(1)(iv). Separately Argued Dependent Claims Regarding dependent claim 5, Appellant argues: 6 As discussed above, “the downlink reception control signal” and “the uplink transmission control signal” may be the same signal. Appeal 2019-004368 Application 15/049,663 20 Claim 5 . . . recites “wherein the downlink reception control signal is comprised of the uplink transmission control signal.” Stratford does not teach this limitation. Page 15 of the Final Office Action cites to paragraphs 0036-0039 of Stratford to reject claim 5. Appellant has reviewed paragraphs 0036-0039 and finds no mention of “wherein the downlink reception control signal is comprised of the uplink transmission control signal,” as recited in claim 5. As discussed above, Stratford does not disclose two control signals – a “downlink reception control signal” and an “uplink transmission control signal.” Claim 5 is thus patentable for this additional reason. Appeal Br. 15. As discussed above with respect to claim 1, and consistent with Appellant’s argument regarding the indefiniteness rejection of claim 5 under 35 U.S.C. § 112, Appellant’s arguments about “two control signals” are unpersuasive. Further, Appellant acknowledges that “Stratford works by sending one signal from the ‘microprocessor 314’ to the ‘switch 312.’” Reply Br. 8 (emphasis omitted). Therefore, the acknowledged Stratford’s signal teaches both the “downlink reception control signal” and “uplink transmission control signal.” As a result, Stratford teaches “the downlink reception control signal is comprised of the uplink transmission control signal,” as required by claim 5. Therefore, and for similar reasons discussed above, we sustain the Examiner’s rejection of dependent claim 5. Regarding dependent claims 10, 11, and 23, Appellant argues: Claim 10 recites “wherein the controller is configured to create a TDD frame timing pattern from the detected uplink/downlink TDD frame configuration and the detected at least one transition in the TDD frame.” Claim 11 depends from Appeal 2019-004368 Application 15/049,663 21 claim 10 and recites “wherein the controller is further configured to synchronize the TDD frame timing pattern with the TDD frame, to determine the at least one uplink frame period in the TDD frame.” Claim 23 has similar limitations to claims 10 and 11. . . . the Office Action cite to paragraphs 0036-0039 and Figures 1-3 of Stratford as allegedly teaching these limitations. Appellant has reviewed the cited portions of Stratford and finds no mention that a “TDD frame timing pattern” is created by the “circuit 300” of Stratford, or that a “TDD frame timing pattern” is synchronized “with the TDD frame” to “determine the at least one uplink frame period in the TDD frame,” as recited in claims 10 and 11, respectively. Stratford simply fails to teach the creation of a “TDD frame timing pattern” by a controller. In the Response to Arguments, page 5 of the Final Office Action states that “the pattern with which the uplink/downlink control signals are send [sic] from the controller 314 is created based on the received downlink signals.” Appellant notes that no portion of Stratford is cited to support this allegation. There is no mention that the ‘‘microprocessor 314” in Stratford (which has been equated to the claimed “controller”) creates a “TDD frame timing pattern.” Thus, claims 10, 11, and 23 are patentable for this additional reason. Appeal Br. 15–16 (emphases omitted). In response to Appellant’s arguments, the Examiner further explains why Stratford discloses the disputed claim limitations: As indicated in Figure 2, the frame timing pattern can be interpreted as “uplink, downlink, uplink, downlink . . . .” This pattern is detected and then used to switch the circuits from uplink mode to downlink mode and back to uplink mode in synchronization with the TDD frame so that the devices can communicate with one another. Examiner . . . asserts that Stratford discloses these limitations. Appeal 2019-004368 Application 15/049,663 22 Ans. 9. Consistent with the Examiner’s above findings, Stratford discloses that microprocessor 314 creates a TDD frame timing pattern: FIG. 3 illustrates one embodiment of a circuit 300 for determining the location in time of a boundary of a transmission structure in communications system 100. In the embodiment shown in FIG. 3, circuit 300 determines the location in time of an end of a subframe based on the power level of signals that are transmitted within system 100. Based on the determined subframe timing, circuit 300 determines when to switch between a TDD downlink mode and a TDD uplink mode. For example, in this embodiment, circuit 300 determines the location in time of the ending boundary for downlink subframe 202. Stratford ¶ 37 (emphases added). When the frame duty cycle is fixed, the end of downlink subframe 202, and thus the start of uplink subframe 204 is fixed relative to start of frame 200. If the location in time of the start of a frame is known . . . the end of the downlink subframe 202 is used to determine the length of downlink subframe 202. From this length the length of uplink subframe 204 and the duty cycle of frame 200 are determined. Once the duty cycle of frame 200 and the start time of frame 200 are known, switching can take place automatically at predetermined times. Stratford ¶ 38 (emphases added). At block 410, the end of downlink subframe 202 is determined by microprocessor 314 from the integrated power curve. Stratford ¶ 50. At block 412, microprocessor 314 uses the information obtained in step 410 to set switch 312 to uplink mode (coupling signals from uplink port 306 to RF duplex port 303) for Appeal 2019-004368 Application 15/049,663 23 subsequent uplink subframes 204. Once microprocessor 314 determines the length of downlink subframe 202 and/or the duty cycle of frame 200, this information is used to set switch 312 to uplink mode at the end of downlink subframe 202. When the duty cycle is fixed, the end time of subsequent downlink subframes can be predicted based on the determined length of downlink subframe 202, because the end of each downlink subframe is the same amount of time from the start of each frame. Thus, in one embodiment, switch 312 is set to switch to uplink mode at the same point in time for every frame. Stratford ¶ 54 (emphases added). Appellant fails to persuasively respond to the Examiner’s further findings and, therefore, fails to show Examiner error. See In re Baxter Travenol Labs., 952 F.2d 388, 391 (Fed. Cir. 1991) (“It is not the function of this court [or this Board] to examine the claims in greater detail than argued by an appellant, looking for [patentable] distinctions over the prior art.”). Therefore, and for similar reasons discussed above, we sustain the Examiner’s rejection of dependent claims 10, 11, and 23. CONCLUSION We affirm the Examiner’s decision rejecting claims 1–24 under 35 U.S.C. § 102. We reverse the Examiner’s decision rejecting claim 5 under 35 U.S.C. § 112(b). Because we affirm at least one ground of rejection with respect to each claim on appeal, we affirm the Examiner’s decision rejecting claims 1–24. See 37 C.F.R. § 41.50(a)(1). Appeal 2019-004368 Application 15/049,663 24 In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 5 112(b) Indefiniteness 5 1–24 102 Stratford 1–24 Overall Outcome 1–24 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R. § 41.50(f). AFFIRMED Copy with citationCopy as parenthetical citation