ATopTech, Inc.v.Synopsys, Inc.Download PDFPatent Trial and Appeal BoardJan 21, 201509481750 (P.T.A.B. Jan. 21, 2015) Copy Citation Trials@uspto.gov Paper 9 571-272-7822 Entered: January 21, 2013 UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ ATOPTECH, INC., Petitioner, v. SYNOPSYS, INC., Patent Owner. ____________ Case IPR2014-01160 Patent 6,405,348 B1 ____________ Before TRENTON A. WARD, PETER P. CHEN, and FRANCES L. IPPOLITO, Administrative Patent Judges. IPPOLITO, Administrative Patent Judge. DECISION Denying Institution of Inter Partes Review 37 C.F.R. § 42.108 IPR2014-01160 Patent 6,405,348 B1 2 I. INTRODUCTION Petitioner ATopTech Inc. filed a Petition on July 11, 2014, requesting an inter partes review of claims 1–28 of U.S. Patent No. 6,405,348 B1 (Ex. 1001, “the ’348 patent”). Paper 2 (“Pet.”). Patent Owner Synopsys, Inc. timely filed a Preliminary Response to the Petition. Paper 8 (“Prelim. Resp.”). We have statutory authority under 35 U.S.C. § 314, which provides that an inter partes review may be authorized only if “the information presented in the petition . . . and any [preliminary] response . . . shows that there is a reasonable likelihood that the petitioner would prevail with respect to at least one of the claims challenged in the petition.” 35 U.S.C. § 314(a). For the reasons described below, we determine that the present record fails to show a reasonable likelihood Petitioner will prevail in showing the unpatentability of any challenged claim. Accordingly, we deny institution as to the challenged claims of the ’348 patent. A. Related Proceedings The ’348 patent is involved in a district court proceeding in the U.S. District Court for the Northern District of California, captioned Synopsys, Inc. v. ATopTech, Inc., Case No. 3:13-cv-02965-MMC (N.D. Cal. 2013). Pet. 1; Paper 6, 1. Petitioner has filed Petitions challenging the patentability of certain claims of Patent Owner’s US Patent Nos. 6,237,127 (IPR2014- 01145), 6,567,967 (IPR2014-01150 and IPR2014-01159), and 6,507,941 (IPR2014-01153). B. The ’348 Patent The ’348 patent discloses a method for performing static timing analysis of digital electronic circuits in the presence of crosstalk. Ex. 1001, IPR2014-01160 Patent 6,405,348 B1 3 Abstract. When two nets of a circuit are placed close to each other, the switching of one net may affect a signal in the other net. Id. at 3:4–8, 7:12– 35. This is referred to as cross-coupling and crosstalk. Id. In some cases, cross-coupling or crosstalk may affect the timing of a net or path. Ex. 1001, 3:4–15. The ’348 patent describes the net affected as the primary net or victim net, and the net causing the crosstalk is referred to as the aggressor net. Ex. 1001, 6:61–63. Additionally, switching in one net may cause a bump-like fluctuation or waveform in the other net. Ex. 1001, 7:20–24; Fig. 4. The ’348 patent further discloses a “bump envelope” method for determining the worst case switching time of an aggressor net. Ex. 1001, 11:10–12. The “bump envelope” method includes the step of identifying a primary net and one or more aggressor nets. Ex. 1001, 11:15–21. To identify these nets, the ’348 patent discloses simulation steps to generate a main output response of the primary net and a bump-like waveform on the output of the primary net. Id. at 3:56–68, 11:27–39. The ’348 patent discloses that the bump-like waveform represents voltage fluctuations on the output of the primary net caused by the switching of the input of the aggressor net. Id. If more than one aggressor net is present, then inputs of the aggressors are switched one at a time to determine multiple bump-like waveforms. Id. at 11:40–43. Once the bump-like waveforms have been generated, a “bump envelope” waveform is determined for each aggressor net. Id. at 11:44–45. The ’348 patent indicates that bump envelopes are obtained by stretching the bump-like waveform for the duration of the aggressor timing or switching window. Id. at 3:58–61, 11:45–48. As an example, Figures 7A–7B are reproduced below. IPR2014-01160 Patent 6,405,348 B1 4 Figure 7A shows primary waveform 710 and bump-like waveform 720. Figure 7B shows bump-like waveform 720 stretched over an aggressor switching window to form bump envelope waveform 730. Ex. 1001, 11:30– 31, 34–39, 45–49. For multiple bump-like waveforms, each bump-like waveform is stretched to form a bump envelope waveform. Id. at 11:53–55. All the bump envelope waveforms are combined to form “an accumulative bump envelope.” Id. at 11:55–57. The ’348 patent further discloses that a composite waveform is generated by super-positioning the bump envelope over the primary waveform. Referring to Figure 7C, the ’348 patent describes generating composite waveform 740 by super-positioning bump envelope 730 on primary waveform 710. Ex. 1001, 11:59–61. Figure 7C is reproduced below. IPR2014-01160 Patent 6,405,348 B1 5 Figure 7C shows threshold voltage 744 at 1.65V and a delay threshold voltage crossing point where composite waveform 740 crosses the threshold voltage. Ex. 1001, 11:63–67. The ’348 patent discloses the delay threshold voltage crossing point corresponds to the time it takes the composite waveform to reach a threshold voltage level. Id. at 11:64–67. The ’348 patent further teaches the worst case switching time is determined by subtracting an amount of time (Δt) that it takes the aggressor response to reach its peak voltage point from the delay threshold voltage crossing point. Id. at 12:8–16. C. Illustrative Claim Of the challenged claims, claims 1, 8, 15, and 22 are independent. Claim 1 reproduced below is illustrative of the subject matter of the ’348 patent: IPR2014-01160 Patent 6,405,348 B1 6 1. In a computer system, a method of analysing crosstalk effects on inerconnects of an integrated circuit design represented as a netlist, the method comprising the steps of: a) accessing a netlist and identifying a cross-coupled circuit contained therein, wherein said cross-coupled circuit includes a primary net and an aggressor net; b) generating a primary waveform of said cross-coupled circuit; c) generating a bump-envelope waveform of said cross- coupled circuit; d) super-positioning said primary waveform over said bump-envelope waveform to generate a composite waveform; e) determining a threshold voltage crossing point of said composite waveform; and f) determining a worst case aggressor switching time based on said threshold voltage crossing point. D. The Asserted Ground Petitioner asserts that the challenged claims are unpatentable under 35 U.S.C. § 103 over Gross1, Dartu2, and Shepard3. II. ANALYSIS A. Claim Construction In an inter partes review, claim terms in an unexpired patent are given their broadest reasonable construction in light of the specification of the patent in which they appear. See 37 C.F.R. § 42.100(b); see also Office 1 Paul D. Gross, Determination of Worst-Case Aggressor Alignment for Delay Calculation, IEEE, 1998 (Ex. 1006, “Gross”). 2 Florentin Dartu et al., Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling, IEEE, 1997 (Ex. 1007, “Dartu”). 3 K. L. Shepard et al., Global Harmony: Coupled Noise Analysis for Full- Chip RC Interconnect Networks, IEEE, 1997 (Ex. 1008, “Shepard”). IPR2014-01160 Patent 6,405,348 B1 7 Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012). Under the broadest reasonable construction standard, claim terms are given their ordinary and customary meaning, as would be understood by one of ordinary skill in the art in the context of the entire disclosure. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special definition for a claim term must be set forth with reasonable clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). 1. bump-envelope waveform (claims 1, 8, 15, and 22) Petitioner proposes a claim construction for the term “bump envelope waveform” recited in independent claims 1, 8, 15, and 22. Pet. 7. Specifically, Petitioner submits the ’348 patent defines a “bump-envelope waveform” as “[a] bump waveform that has been stretched along a predetermined aggressor switching window.” Id. (citing Ex. 1001, 11:45– 49. Petitioner’s proposed construction adopts the additional limitations required in dependent claim 6 as the definition for the “bump envelope waveform” recited in claim 1. Pet. 44–45. Patent Owner does not propose a construction. On the present record, however, we are not persuaded that Petitioner’s proposal of a “predetermined aggressor switching window” is fully consistent with the broader description in the Specification of the ’348 patent. The Specification states that “a bump envelope is created for each aggressor by stretching the bump-like waveform for the duration of the aggressor timing window.” Ex. 1001, 3:58–61. For a particular embodiment described in Figures 7A–7C, the Specification discloses that “bump envelopes are obtained by stretching the bump-like waveform (e.g., IPR2014-01160 Patent 6,405,348 B1 8 waveform 720) for the size of the switching window.” Ex. 1001, 11:46–48. Thus, we are not persuaded that the language of claim 6 requires the “bump envelope waveform” of claim 1 to be stretched along a predetermined aggressor switching window. Accordingly, based on the current record, we construe the term “bump-envelope waveform” as “a bump waveform that has been stretched for the duration of an aggressor timing window.” 2. Means-Plus-Function Limitations Claims 15–21 include means-plus-function limitations. These limitations require construction under 35 U.S.C. § 112, ¶ 6, which states such claims “shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.” 35 U.S.C. § 112, ¶ 6.4 For means-plus-function limitations where the corresponding structure is a computer, the Federal Circuit has held that the specification must disclose the specific algorithm used by the computer to perform the recited function. WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349 (Fed. Cir. 1999) (“In a means-plus-function claim in which the disclosed structure is a computer, or microprocessor, programmed to carry out an algorithm, the disclosed structure is not the general-purpose computer, but rather the special purpose computer programmed to perform the disclosed algorithm.”). The Specification “can express the algorithm in any understandable terms including as a mathematical formula, in prose, or 4 Section 4(c) of the Leahy-Smith America Invents Act (AIA) re-designated § 112, ¶ 6, as § 112(f). Pub. L. No. 112-29, 125 Stat. 284, 296 (2011). Because the ’348 patent has a filing date before September 16, 2012 (effective date), we will refer to the pre-AIA version of § 112. IPR2014-01160 Patent 6,405,348 B1 9 as a flow chart, or in any other manner that provides sufficient structure.” Finisar Corp. v. DirecTV Grp., 523 F.3d 1323, 1340 (Fed. Cir. 2008). If the Specification fails to provide sufficient structure, the means-plus-function limitation is indefinite. Aristocrat Techs. Australia Pty Ltd. v. Int’l Game Techs., Inc., 521 F.3d 1328, 1333 (Fed. Cir. 2008). Petitioner has not proposed constructions for any of the means-plus- function limitations recited in independent claim 15 and dependent claims 16–21. Without addressing these claim construction considerations, Petitioner essentially requests the Board to construe the “means-plus- function” limitations of the claims sua sponte, and then apply the art. It is Petitioner, however, who must demonstrate a reasonable likelihood that a claim is unpatentable including indicating how a challenged claim is to construed. 37 C.F.R. §42.104(b)(3) (“[w]here the claim to be construed contains a means-plus-function or step-plus-function limitation as permitted under 35 U.S.C. 112(f), the construction of the claim must identify the specific portions of the specification that describe the structure, material, or acts corresponding to each claimed function”). Thus, we decline to construe the “means-plus-function” limitations, which required further analysis that Petitioner failed to provide. B. Claims 1–28 – Asserted Obviousness over Gross (Ex. 1006), Dartu (Ex. 1007), and Shepard (Ex. 1008) We have considered the arguments and evidence presented, and are not persuaded that there is a reasonable likelihood that Petitioner would prevail on its assertion that claims 1–28 would have been obvious in view of Gross, Dartu, and Shepard. IPR2014-01160 Patent 6,405,348 B1 10 1. Summary of Gross (Ex. 1006) Gross teaches crosstalk or coupling between adjacent lines in ICs (integrated circuits) can “dramatically” affect IC performance as dimensions become increasingly smaller and enter the Deep Submicron Region (“DSM”). Ex. 1006, 6. “Gates driving parallel lines at these dimensions will strongly impact one another due to the coupling.” Id. Gross further discloses when coupling capacitance between adjacent lines is dominant, the switching in aggressor gates can induce a large amount of noise on the victim line. Id. Gross adds that if aggressor and victim lines switch in the same direction, the victim will speed up, and if the lines switch in opposite directions, the victim will slow down. Id. As a solution to timing problems resulting from coupling, Gross proposes a “waveform iteration methodology to obtain the aggressor alignment that induces worst-case delay on the victim.” Id. Gross further teaches “[c]omputing the worst-case delays for a path in timing analysis corresponds to calculating the worst-case delays for each of the logic stages (dc coupled components, or gates and their associated interconnect) that comprise that path.” Id. Figures 7 and 8 are reproduced below. Figure 7 depicts an example of coupled paths, where V denotes the victim line and A refers to the aggressor line. Ex. 1006, 11. Gross teaches IPR2014-01160 Patent 6,405,348 B1 11 that the victim waveform is denoted by Vk(t) and k refers to the kth waveform iteration with V1(t) being the first victim waveform generated with a quiet aggressor line. Id. Gross further defines the noise on the victim line at the kth waveform iteration as the difference between Vk(t) and V1(t). Id. Figure 8 shows the victim waveforms for V1(t) and V2(t). The difference V2N is the maximum difference between V2(t) and V1(t), separately for each aggressor (all other aggressors quiet). Id. Figure 8 further shows time t1N for when the maximum voltage displacement of the noise V2N occurs between the V2(t) and V1(t). Ex. 1006, 11. Gross discloses time t2N when V1(t) crosses the voltage threshold xVDD minus V2N. Id. Additionally, Gross teaches shifting the aggressor’s input by t2N-t1N. Id. 2. Dartu (Ex.1007) Dartu is directed to calculating worst-case gate delays due to dominant capacitance coupling. Ex. 1007, Title. To illustrate Dartu’s described calculation, Figures 10 and 11 are reproduced below. Figure 10 shows waveforms resulting from coupled paths. Ex. 1007, 5. Figure 10 includes the original signal (i.e., victim signal), a noise signal, and a composite signal. Figure 11 shows the worst case delay for the composite signal in Figure 10 corresponds to the time, tM in Figure 11 when the original signal crosses 0.5-VN. Dartu explains the described worst-case IPR2014-01160 Patent 6,405,348 B1 12 delay calculation computes (1) “VN which is a simpler optimization goal than calculating tdf . . .,” and (2) the time when the original signal crosses (0.5-VN). Ex. 1007, 6. 3. Shepard (Ex. 1008) Shepard teaches methods to deal with coupled noise in timing analysis. Ex. 1008, 5. Shepard teaches that the static timing analysis may be linked with the static noise analysis such that each considers information from the other. Id. at 9 (“This enables timing information to be used in the calculation of noise and noise information to be used in the calculation of timing.”). Shepard further teaches that the static noise added to a receiver may be bounded by the timing windows of the nets involved. Id. (“Timing windows, as defined by the earliest and latest possible arrival time, are determined for each secondary net driver. This allows us to calculate the worst possible noise in the presence of arrival time constraints, reducing pessimism in the analysis.”). Shepard teaches linking the static timing analysis with the noise analysis by performing an initial timing analysis and then freezing the arrival time windows and slews at each driver. Ex. 1008, 10. Shepard teaches noise peaks that fall within the timing windows, should be considered. Id. 4. Analysis a. Claims 1–14 and 22–28 Petitioner contends that Gross, Dartu, and Shepard teach or suggest all the limitations of claims 1–14 and 22–28. Pet. 11–46. Below we discuss independent claim 1, which is illustrative of independent claims 8 and 22 and dependent claims 2–7, 9–14, and 23–28. Claim 1 is directed to a “method of analysing crosstalk effects on IPR2014-01160 Patent 6,405,348 B1 13 interconnects of an integrated circuit design represented as a netlist” that includes the step of “c) generating a bump-envelope waveform of said cross- coupled circuit.” (Emphasis added). For this limitation, Petitioner concedes that “Gross does not disclose stretching the bump waveform to create a bump envelope waveform. Ex. 1009, ¶75.” Pet. 20 (emphasis added); see also Pet 31 (“Gross teaches all the limitations of claims 1, 8, 15, and 22 of the ‘348 patent except generating the ‘bump envelope waveform.’”). Petitioner then asserts that Dartu and Gross teach calculating the maximum voltage VN of the aggressor waveform and adding VN to the primary waveform of the victim net. Id. (referring to Figures 10 and 13 from Dartu). Petitioner contends this concept is the “real invention” and the ’348 patent “simply implements the concepts taught by Dartu and proven by Gross.” Id. at 34. Petitioner adds that the “concept of ‘stretching’ the bump waveform over the switching window is a red he[r]ring and is in fact nothing but a fancy name for a direct current (DC) offset. Ex. 1009, ¶109.” Id. at 35 (emphasis added). With respect to Shepard, Petitioner asserts Shepard teaches that static noise added to a receiver may be bounded by the timing windows of the nets involved. Pet. 36 (citing Ex. 1008, 9–10). Petitioner adds that a skilled artisan would know “that if they did not know at what temporal location to add ΔV to the primary waveform, they could simply add it over the entire ‘switching window’ as taught by Shepard.” Pet. 38 (citing Ex. 1009 ¶ 117). On the present record, we are not persuaded by Petitioner’s position that “generating the bump-envelope waveform” is a mere red herring and “a fancy name for a direct current (DC) offset.” Pet. 31, 35. As Petitioner points out, Gross and Dartu do not even disclose a DC offset because Gross IPR2014-01160 Patent 6,405,348 B1 14 and Dartu “do not need to add ΔV across a large portion of the primary waveform because they teach exactly where to add ΔV.” Pet. 35 (emphasis added). Referring to Figures 7A and 7B from the ’348 patent annotated by the Petitioner (reproduced below), Petitioner explains the figure on the left illustrates Gross and Dartu’s disclosed method of adding ΔV to a specific location on the primary waveform, and the figure on the right depicts a DC offset added to primary waveform 710. Id. The annotations on Figures 7A and 7B are shown mainly in red with the exception of the overlay of primary waveform 710 from Figure 7A onto Figure 7B. Despite Petitioner’s attempts to annotate Figures 7A and 7B of the ’348 patent, Petitioner fails to identify any disclosure in the ’348 patent regarding a DC offset or how ‘stretching’ the bump waveform over the switching window is similar to a DC offset. Furthermore, Petitioner acknowledges Gross and Dartu do not disclose a DC offset and Petitioner does not explain where a DC offset is disclosed in the only remaining prior art reference, Shepard. Instead, Petitioner relies on Dr. Soheil Ghiasi’s conclusory testimony that it would have been obvious to modify Gross or Dartu to include a DC offset “if you did not want to calculate the intersection point, you could [] instead added ΔV across the entire primary wave with the same IPR2014-01160 Patent 6,405,348 B1 15 result.” Id. (citing Ex. 1009 ¶ 108). However, the cited passages of Dr. Ghiasi’s declaration only mirror the corresponding text of the Petition and do not provide any factual basis for their assertions and are, therefore, entitled to little weight. Rohm and Haas Co. v. Brotech Corp., 127 F.3d 1089, 1092 (Fed. Cir. 1997) (“Nothing in the rules or in our jurisprudence requires the fact finder to credit the unsupported assertions of an expert witness.”); see also 37 C.F.R. §42.65(a) (“[e]xpert testimony that does not disclose the underlying facts or data on which the opinion is based is entitled to little or no weight.”). Moreover, without an underlying factual basis to support Petitioner’s proposed modification to Gross and Dartu, these arguments amount to “mere conclusory statements” that cannot support an obviousness rejection. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (citing In re Kahn, 441 F.3d 977, 988 (2006)). Additionally, we also are not persuaded by Petitioner’s assertion that “[o]ne skilled in the art would also know that if they did not know at what temporal location to add ΔV to the primary waveform, they could simply add it over the entire ‘switching window’ as taught by Shepard.” Pet. 38 (citing Ex. 1009 ¶ 117). Petitioner has not explained sufficiently how adding ΔV across the entire primary waveform, shown as a series of red arrows added by Petitioner’s annotations to Figure 7B of the ’348 patent shown on the right above, teaches a bump-envelope waveform or generating such a waveform. The waveforms represented by dotted lines in the annotated figures above appear to show a modified primary waveform, not a bump-envelope waveform, resulting from the addition of ΔV to primary waveform 710. Regardless, these are annotations of the figures to the ’348 patent and not to prior art references relied upon by Petitioner’s challenge. IPR2014-01160 Patent 6,405,348 B1 16 Accordingly, upon consideration of the Petition, Preliminary Response, and evidence presented, we conclude that Petitioner has not established a reasonable likelihood of prevailing on its assertion that claim 1 and its dependent claims 2–7 would have been obvious over Gross, Dartu, and Shepard. Further, independent claim 8 recites the step of “c) generating a bump-envelope waveform of said cross-coupled circuit,” and independent claim 22 recites the steps of “c) generating bump-envelope waveforms of said cross-coupled circuit” and “d) generating an accumulative bump- envelope by super-positioning said bump-envelope waveforms.” Petitioner relies on the same arguments discussed above for its assertion that these claims and their dependents would have been obvious over the asserted combination. For the same reasons discussed above, we are not persuaded that Petitioner has demonstrated that there is a reasonable likelihood that it would prevail with respect to claims 8–14 and 22–28 on this ground. b. Claims 15–21 Petitioner contends that Gross, Dartu, and Shepard teach or suggest all the limitations of claims 15–21. Pet. 11–46. Below we discuss independent claim 15, which is illustrative of dependent claims 16–21. Independent claim 15 is directed to a computer-implemented electronics design automation system and includes seven (7) means-plus- function limitations: means for accessing a netlist representative of an integrated circuit design; means for identifying a cross-coupled circuit contained within said netlist, wherein said cross-coupled circuit includes a primary net and an aggressor net; first simulation means for generating a primary waveform of IPR2014-01160 Patent 6,405,348 B1 17 said cross-coupled circuit; second simulation means for generating a bump-envelope waveform of said cross-coupled circuit; means for super-positioning said primary waveform over said bump-envelope waveform to generate a composite waveform; first calculation means for determining a threshold voltage crossing point of said composite waveform; and second calculation means for determining a worst case aggressor switching time based on said threshold voltage crossing point. (emphasis added). As explained above, Petitioner has not identified sufficient structure (e.g., identified a microprocessor programmed to perform a specific algorithm) to meet their burden under Rule 104(b)(3). That is, to the extent such an algorithm exists, Petitioner has not “identif[ied] the specific portions of the specification that describe the structure . . .corresponding to each claimed function.” 37 C.F.R. § 42.104(b)(3). Further, while we observe that Figure 9 of the ’348 patent discloses what appears to be mathematical equations used to describe the problem of determining the worst case switching time of the aggressors, (Ex. 1001:5:12–14), it is unclear on the present record whether Petitioner relies on the disclosed mathematical equations to describe a specific algorithm that performs one or more of the functions recited in claim 15. We decline to speculate on the specific disclosure in the ’348 patent that describes an algorithm or structure corresponding to all seven (7) means-plus-function limitations recited in claim 15. IPR2014-01160 Patent 6,405,348 B1 18 Moreover, because Petitioner has failed to provide sufficient structure for the claim construction, Petitioners have failed to specify where this structure is found in Gross, Dartu, and Shepard, pursuant to 37 C.F.R. § 42.104(b)(4). Accordingly, we decline to institute trial on claims 15–21. Cf. Blackberry Corp. v. MobileMedia Ideas, LLC, IPR2013-00036, slip op. at 12-21 (PTAB Mar. 7, 2014) (Paper 65) (terminating IPR proceeding where Board was unable to reach a determination on the grounds of unpatentability because the specification did not disclose a specific algorithm with which to program the microprocessor to achieve the function of the means-plus-function limitation). We further note that claim 15 recites “second simulation means” that performs the function of “generating a bump-envelope waveform of said cross-coupled circuit.” Petitioner relies on the same arguments discussed above in Section II. B. 4. a. for this limitation. Pet. 18–20, 31–38. For the same reasons discussed above, we are not persuaded Petitioner has demonstrated sufficiently that Gross, Dartu, and Shepard teach or suggest “generating a bump-envelope waveform of said cross-coupled circuit.” Accordingly, based on the present record, we conclude that Petitioner has not established a reasonable likelihood of prevailing on its assertion that claim 15 and its dependent claims 16–21 would have been obvious over Gross, Dartu, and Shepard. III. CONCLUSION For the foregoing reasons, we conclude that Petitioner has not demonstrated a reasonable likelihood that claims 1–28 of the ’348 patent are unpatentable. IPR2014-01160 Patent 6,405,348 B1 19 IV. ORDER In consideration of the foregoing, it is hereby: ORDERED that the Petition is denied. PETITIONER: Jeffrey A. Miller Paul G. Novak DICKSTEIN SHAPIRO LLP millerj@dicksteinshapiro.com novakp@dicksteinshapiro.com PATENT OWNER: David Cochran Joseph Sauer David W. Wu JONES DAY dcochran@jonesday.com jmsauer@jonesday.com dwwu@jonesday.com Copy with citationCopy as parenthetical citation