ARM Limited

Patent Trials and Appeals Board

Feb 15, 2022

2020004989 (P.T.A.B. Feb. 15, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/007,529 01/27/2016 Viswanath CHAKRALA JRL-550-1946 5972 73459 7590 02/15/2022 NIXON & VANDERHYE, P.C. 901 NORTH GLEBE ROAD, 11TH FLOOR ARLINGTON, VA 22203 EXAMINER BRAGDON, REGINALD GLENWOOD ART UNIT PAPER NUMBER 2139 NOTIFICATION DATE DELIVERY MODE 02/15/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): PTOMAIL@nixonvan.com pair_nixon@firsttofile.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte VISWANATH CHAKRALA and ANDREW BROOKFIELD SWAINE Appeal 2020-004989 Application 15/007,529 Technology Center 2100 Before TREVOR M. JEFFERSON, GREGG I. ANDERSON, and CHRISTA P. ZADO, Administrative Patent Judges. ANDERSON, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1-13 and 15-16. Final Act.2 4, 13, and 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as ARM, Limited. Appeal Br. 3. 2 We use “Spec.” to refer to the Specification filed January 27, 2016, as amended May 21, 2018; “Final Act.” to refer to the Final Office Action mailed October 1, 2019; “Appeal Br.” to refer to the Appeal Brief filed March 2, 2020; “Ans.” to refer to the Examiner’s Answer filed April 22, 2020; and “Reply Br.” to refer to the Reply Brief filed June 22, 2020. Appeal 2020-004989 Application 15/007,529 2 17. Appellant appeals the rejection of claims 1-13 and 15-16. Appeal Br. 7-11, 12-17 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b). We affirm. CLAIMED SUBJECT MATTER The invention is directed to data processing as “it relates to the translation of addresses between a first set of addresses and a second set of addresses.” Spec. 23:4-6. An apparatus is described for data processing on “data items stored in a memory and retrieved via a memory hierarchy.” Id. at 5:11-13. If an address translation between the first set address and the second set address is stored in the address translation storage a second set address is returned in response to a request for data processing. Id. at 5:15- 18. If the second address is not stored in address translation storage, the request is forwarded “towards the memory in the memory hierarchy.” Id. at 5:18-20. “[A]ddress translation in a data processing apparatus may suffer from capacity or bandwidth problems.” Spec. 5:27-30. A translation control unit (TCU) comprising a level2 (L2) translation lookaside buffer (TLB) may become a bottleneck, when the TCU receives address translation requests forwarded to it from multiple level 1 (L1) TLBs because the time required to perform the lookups. Id. at 5:30-6:4. The Specification explains this problem is addressed with pending request storage. Id. at 6:9-10. Pending request storage stores previous requests and is responsive to reception of the request. Spec. 5:20-22. “[P]ending request storage can 3 The Specification lacks page numbers. Page 2 has been assigned to the page including the “Technical Field,” “Background,” and “Summary” headings. Further pages are numbered sequentially from page 2. Appeal 2020-004989 Application 15/007,529 3 relieve capacity pressure without degrading performance.” Id. at 6:23-24. If “a stored entry for a previous request indicates the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation” a request may be intercepted “to delay its reception by the address translation storage.” Id. at 5:22-26. By “intercepting a request where it is known that the expected response for an earlier request will provide the required address translation” and (temporarily) holding it back from progressing further until that response is received. Id. at 6:24-27. “Once received, both the earlier request and the later request can then be directly responded to.” Id. at 6:27- 28. Claims 1 and 16 are independent apparatus claims and claim 15 is an independent method claim. Claims 2-13 depend from claim 1. Claim 1, reproduced below, illustrates the claimed subject matter: 1. Apparatus for data processing comprising: data processing circuitry to perform data processing operations on data items stored in a memory and retrieved via a memory hierarchy; address translation storage to store address translations between first set memory addresses and second set memory addresses, wherein the address translation storage is responsive to a request issued by the data processing circuitry comprising a first set memory address to return a response comprising a second set memory address if an address translation between the first set memory address and the second set memory address is stored in the address translation storage, and to forward the request towards the memory in the memory hierarchy if the address translation between the first set memory address and the second set memory address is not stored in the address translation storage; and Appeal 2020-004989 Application 15/007,529 4 pending request storage to store entries for received requests, wherein the pending request storage is responsive to reception of the request, to perform a memory address comparison of the first set memory address of the request with the first set memory address of an earlier request indicated by a stored entry of the pending request storage, and if the memory address comparison is indicative that the earlier request has been forwarded towards the memory and an expected response to the earlier request will provide the address translation, to intercept the request to delay its reception by the address translation storage. Appeal Br. 12 (Claims App.). REFERENCES The Examiner relies on the following references. Name4 Reference Date5 Andersson US 2002/0144077 A1 Oct. 3, 2002 Kong US 2012/02908813 A1 Nov. 15, 2012 Zhang US 9,619,402 B1 Nov. 26, 2013 Spadini US 2014/0380024 A1 Dec. 25, 2014 REJECTION Claims 1-7 and 15-16 are rejected under 35 U.S.C. §103 as unpatentable over Zhang and Andersson. Final Act. 4-12. Claims 8 and 10-13 are rejected under 35 U.S.C. §103 as unpatentable over Zhang, Andersson and Spadini. Final Act. 13-17. Claim 9 is rejected under 35 U.S.C. §103 as unpatentable over Zhang, Andersson and Kong. Final Act. 4-12. 4 All reference citations are to the first named inventor only. 5 Publication date except for Zhang which is filing date. Appeal 2020-004989 Application 15/007,529 5 STANDARD OF REVIEW The Board conducts a limited de novo review of the appealed rejections for error based upon the issues identified by Appellant, and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). Arguments not made are waived. See id.; 37 C.F.R. § 41.37(c)(1)(iv) (2019). CONTENTIONS AND ANALYSIS Issue: Does Zhang teach “if the memory address comparison is indicative that the earlier request has been forwarded towards the memory and an expected response to the earlier request will provide the address translation, to intercept the request to delay its reception by the address translation storage6” (“interception limitation”), as recited in claim 1? The Examiner’s Findings The Examiner finds the interception limitation is taught by Zhang, which performs a memory address comparison between the first set memory address and a “memory address of an earlier request indicated by a stored entry of the pending request storage.” Final Act. 5-6 (citing Zhang, 1:57- 2:22, 2:55-3:8, 3:43-67, 6:50-66, Fig. 4). In response to Appellant’s argument that claim 1 is not taught because Zhang’s translation look-aside buffer (TLB) precedes interception in Zhang precedes reception by Zhang’s memory translation buffer (MTB) and does not delay reception of the request by the MTB, the Examiner finds Zhang teaches that “[w]hen there are multiple table walk requests, dependencies may be established in that matching portions of virtual memory addresses 6 The bolded language framing the issue before us. Appeal 2020-004989 Application 15/007,529 6 may be present between an older pending table walk request and a younger table walk request.” Ans. 17 (citing Zhang, 3:43-67, 6:50-66, 6:50-66, Fig.4). The Examiner further contends The data that is fetched from memory in response to the request will make its way back to the TLB. This is what Andersson was brought in to support in the rejection . . . Therefore this hold will delay its reception at the TLB (address translation storage). Id. (citing Andersson ¶ 35, Fig. 1). Appellant’s Contentions Appellant argues the interception limitation is not taught by Zhang because claim 1 requires that the “TLB 102 (‘address translation storage’) precedes rather than follows the memory translation buffer (MTB) 106 (‘pending request storage’).” Appeal Br. 7-8 (citing Zhang Fig. 1). Appellant further contends that “[a]s a result, it is too late to delay reception of the request by the TLB 102 (mapped by the Examiner to the claimed address translation storage) because the request has already been received by the TLB 102 and missed.” Id. at 8 (citing Zhang, 3:48-55). This is contrary to claim 1 which Appellant alleges “causes the second address translation request to be delayed by the address translation storage so that an address translation storage hit can occur to avoid the need for a second page walk.” Reply Br. 4; see also Zhang, 3:9-12 (“searching a page table is a process called a table walk or search”) (emphasis added). Appellant argues that the Examiner’s misunderstands Zhang’s “hold” and how Andersson fetches data for the TLB in response to the request. Reply Br. 5. Appellant argues that “[c]laim 1 does not recite that reception Appeal 2020-004989 Application 15/007,529 7 of the data returned by the table walk request is delayed” but rather the “request issued by the data processing circuitry” for the data is delayed. Id. Analysis For purposes of this decision, we adopt the Examiner’s findings as ours. The following discussion summarizes those findings. We are not persuaded that Zhang’s request is intercepted prior to receipt by the TLB, as per claim 1’s recitation “to day reception by the address translation storage,” i.e., Zhang’s TLB. Zhang’s Figure 1 is not cited in support of the rejection but that younger table “walks or searches” only after completion of prior, older, “table walk requests.” Ans. 17. Rather the Examiner points to the hold that Zhang teaches regarding precedes reception by Zhang’s memory translation buffer (MTB). Id. (citing Zhang, 3:43-67, 6:50-66, Fig. 4). Contrary to Appellant’s contention, the request, as opposed to the requested data, is what Zhang “holds,” i.e., delays. “MTB 106 only advances a younger table walk request to a table walk of page table 104 after completion of a table walk for the older table walk request.” Zhang, 4:30-31; Ans. 17. Thus, we agree with the Examiner’s findings that Zhang teaches the interception limitation. Ans. 17. CONCLUSION For the reasons discussed above, the rejection to claim 1 is sustained. Appellant argues independent claims 15 and 16 based on its arguments for claim 1. Appeal Br. 10. The dependent claims are not separately argued. Accordingly, the rejections to claims 1-13 and 15-16 are sustained. Appeal 2020-004989 Application 15/007,529 8 DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-7, 15-16 103 Zhang, Andersson 1-7, 15-16 8, 10-13 103 Zhang, Andersson, Spadini 8, 10-13 9 103 Zhang, Andersson, Kong 9 Overall Outcome 1-13, 15-16 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED