Apple Inc.

Patent Trials and Appeals Board

Mar 31, 2020

14496934 - (D) (P.T.A.B. Mar. 31, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/496,934 09/25/2014 Liang Xia 8888-44900 6507
81310 7590 03/31/2020
Kowert Hood Munyon Rankin & Goetzel (Apple)
P.O. BOX 398
Austin, TX 78767-0398
EXAMINER
SALVUCCI, MATTHEW D
ART UNIT PAPER NUMBER
2613
NOTIFICATION DATE DELIVERY MODE
03/31/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patent_docketing@intprop.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LIANG XIA, ROBERT D. KENNEY,
BENJIMAN L. GOODMAN, and TERENCE M. POTTER
Appeal 2019-000772
Application 14/496,934
Technology Center 2600
Before CAROLYN D. THOMAS, JASON V. MORGAN, and
SCOTT RAEVSKY, Administrative Patent Judges.
RAEVSKY, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–4, 6–9, 11–15, and 17–20. We have
jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 We use the word “Appellant” to refer to “Applicant” as defined in
37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Apple
Inc. Appeal Br. 2.
Appeal 2019-000772
Application 14/496,934

2
CLAIMED SUBJECT MATTER
The claims relate to a data queuing and format apparatus. See Spec.,
Abstr. Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. An apparatus, comprising:
a first selection circuit configured to selectively couple
data bits of a first subset of a plurality of data bits conveyed on
a bus to respective data lines of a first plurality of data lines, the
first plurality of data lines being column data lines;
a second selection circuit configured to selectively couple
data bits of a second subset of the plurality of data bits
conveyed on the bus to a respective data line of a second
plurality of data lines, the second plurality of data lines being
row data lines;
a first storage array including a plurality of storage units,
wherein each storage unit of the plurality of storage units is
configured to selectively receive data from at least one data line
of the first plurality of data lines or at least one data line of the
second plurality of data lines such that various bit positions of
the data bits of the first and second subsets are selectively
stored in different relative positions within the first storage
array; and
a second storage array configured to store control
information separately from data stored in the first storage
array, wherein the first and second selection circuits are coupled
to receive control information from the second storage array;
wherein each of the first and second selection circuits is
configured to store data to conform to a data format employed
by a destination of the data.
REJECTION
Claims 1–4, 6–9, 11–15, and 17–20 stand rejected under 35 U.S.C.
§ 103 as being unpatentable over Khailany (US 2014/0136778 A1, May 15,
2014) and Prokopenko (US 2007/0185953 A1, Aug. 9, 2007). Final Act. 3.

Appeal 2019-000772
Application 14/496,934

3
ANALYSIS
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential).
Issue: Did the Examiner err in finding that the combination of
Khailany and Prokopenko teach or suggest “a second storage array
configured to store control information separately from data stored in the
first storage array,” as recited in claim 1? Appeal Br. 13–17; Reply Br. 6–7.
Appellant contends that Khailany fails to teach or suggest this
limitation. Appeal Br. 14. Appellant contends that nothing in Khailany “is
directed to storing control information, much less storing control
information separately from data.” Id. (emphasis omitted). For example,
Appellant contends,
[p]aragraph [0037] [of Khailany] is directed to a single-ended
global write bit line and a number of different control signals of
a control bundle. However, there is no indication in paragraph
[0037] that these control signals comprise control information
that is stored in any array, much less stored in an array
separate from one that stores data.
Id. at 15–16 (emphasis omitted). Appellant also contends that other
disclosure in Khailany fails to teach or suggest the disputed limitation. For
example, Appellant contends that although Khailany paragraph 20 discloses
“separate control may be used for local bit lines and global bit lines, . . . this
paragraph is silent in its entirety with respect to storing control information,
much less separately from data.” Id. at 14 (emphasis omitted).
The Examiner finds that “each of the cited paragraphs [in Khailany]
discusses the separate storage of bits, with [p]aragraph [0037] specifically
discussing that ‘[e]ach sub-array contains a control bundle.’” Ans. 32; see
Appeal 2019-000772
Application 14/496,934

4
also Final Act. 5–6. The Examiner further finds that “[p]aragraph [0020]
discloses that ‘within the storage array, separate control may be used for
local bit lines and global bit lines,’” and that “clearly these separate sub-
arrays within the storage array and the bits in the control bundle of said sub-
array” reads on the disputed limitation. Id. at 32–33. In Reply, Appellant
contends that paragraph 20 is merely directed to providing “separate
control” for global and local read bit lines, while paragraph 37’s control
signals are “not shown as being stored anywhere, much less within the
storage cells of a memory array.” Reply Br. 6–7 (emphasis omitted).
We agree with Appellant. Khailany discloses that “[e]ach sub-array
contains a control bundle,” i.e., control information. Khailany ¶ 37. But
Khailany’s storage sub-arrays also store data. Id. ¶¶ 12 (“storage array may
be used to stage data”), 32 (“write new data into one of the cells in the sub-
array”). Since Khailany’s storage sub-arrays store data and contain control
information, we agree with Appellant that Khailany does not disclose a
second storage array that stores control information separately from data in a
first storage array, as claimed.
We note the Examiner has not relied on any of the other cited
references to teach or suggest this element. Accordingly, we do not sustain
the Examiner’s rejection of claim 1 and its corresponding dependent claims.
Independent claim 7 recites similar language, including “storing the control
information in a first queue” and “storing the subset of the plurality of data
bits into the second queue, the second queue being separate from the first
queue.” Claim 15 also recites similar language, including “store the control
information in a first queue” and “store the portion of the data in a second
queue separate from the first queue.” Accordingly, we also do not sustain
Appeal 2019-000772
Application 14/496,934

5
the Examiner’s rejections of claims 7 and 15 and their corresponding
dependent claims.
We do not reach Appellant’s further allegations of error because we
find the issue discussed above to be dispositive of the rejection of all the
pending claims.
CONCLUSION
In summary:
Claims
Rejected
35 U.S.C. § References Affirmed Reversed
1–4, 6–9,
11–15, 17–20
103 Khailany,
Prokopenko
1–4, 6–9,
11–15, 17–20
REVERSED