Ahmed H. El-Mahdy et al.

Patent Trials and Appeals Board

Apr 1, 2020

15049830 - (D) (P.T.A.B. Apr. 1, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/049,830 02/22/2016 Ahmed H. El-Mahdy FR920080139US2
8152-0265
5807
73109 7590 04/01/2020
Cuenot, Forsythe & Kim, LLC
20283 State Road 7
Ste. 300
Boca Raton, FL 33498
EXAMINER
MACKALL, LARRY T
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
04/01/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ibmptomail@iplawpro.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte AHMED H. EL-MAHDY and
HISHAM EMADELDIN ELSHISHINY
____________________

Appeal 2018-003588
Application 15/049,830
Technology Center 2100
____________________

Before ROBERT L. KINDER, CHRISTA P. ZADO, and
KAMRAN JIVANI, Administrative Patent Judges.

JIVANI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s final rejection of claims 21–40. We have jurisdiction under
35 U.S.C. § 6(b).
We REVERSE.

1 According to Appellant, the real party in interest is IBM Corporation.
App. Br. 1.
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Application 15/049,830

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STATEMENT OF THE CASE
Appellant’s Invention
Appellant’s invention generally relates to “a prefetch controller
configured to dynamically learn and subsequently predict an upcoming
processor request.” Spec. ¶ 1.
Claims on Appeal
Claims 21, 28, and 35 are the independent claims on appeal. Claim 1
is illustrative of the claimed subject matter and is reproduced below, with
bracketed material added:
21. A computer hardware system, comprising:
a data cache;
a prefetch controller configured to[:]
receive an initial tuple including an initial
instruction ID and an initial missed data address,
retrieve a last data access address,
subtract the last data access address from the first
missed data address to generate an instruction/stride
tuple,
generate a predicted prefetch address using the
instruction/stride tuple; and
a prefetch cache configured to[:]
receive, from the prefetch controller, the predicted
prefetch address, and
provide, to the data cache, the predicted prefetch
address.
App. Br. 12.

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Application 15/049,830

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Examiner’s Rejections
The following rejections are before us for review.
1. Claims 21–40 stand rejected for non-statutory obviousness-type
double patenting over claims 1–8 of U.S. Patent No. 9,274,965.
2. Claims 21–25, 27–32, and 34–39 stand rejected under
35 U.S.C. § 103(a) over Puzak (US 5,790,823; issued Aug. 4, 1998) and
McMinn (US 6,138,213; issued Oct. 24, 2000).2

ANALYSIS
Double Patenting Rejection of Claims 21–40
The Examiner rejects all the pending claims for non-statutory
obviousness-type double patenting, stating “[c]laims 1–8 of U.S. Patent
No. 9,274,965 contain every element of claims 21–40 of the instant
application and as such anticipate claims 21–40 of the instant application.”
Final. Act. 3. The Examiner further states, “[a] timely filed terminal
disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to
overcome an actual or provisional rejection based on a nonstatutory double
patenting ground provided the reference application or patent either is shown
to be commonly owned with this application, or claims an invention made as
a result of activities undertaken within the scope of a joint research
agreement.” Id. Appellant represents “that a Terminal Disclaimer has been
filed with regard to U.S. Patent No. 9,274,965.” Reply Br. 2.

2 The Examiner has withdrawn the earlier rejections of claim 26, 33, and 40
in light of Appellant’s arguments during prosecution. Final Act. 14. These
claims, therefore, do not stand rejected on obviousness grounds in the record
before us.
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Application 15/049,830

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Accordingly, in light of Appellant’s representation that a terminal
disclaimer has been filed, we do not reach the merits of the double patenting
rejection. Should prosecution of these claims continue, we leave it to the
Examiner to determine whether the terminal disclaimer overcomes the non-
statutory obviousness-type double patenting rejection in light of the
guidance provided in MPEP §§ 706.02, 717.02.
Obviousness Rejections of Claims 21–25, 27–32, and 34–39
Claim 21 recites in relevant part, “a prefetch controller configured to
. . . subtract the last data access address from the initial missed data address
to generate an instruction/stride tuple.” App. Br. 12.
The Examiner finds Puzak teaches the claim limitation at issue
because Puzak’s “stride is the distance between the last miss and the most
recent miss.” Final Act. 5 (citing Puzak, 7:61–67). The Examiner continues
by mapping the claim elements as follows: “the ‘last operand miss’ refers to
the claimed ‘initial missed data address’ and the ‘most recent miss’ refers to
the ‘last data access address.’” Id. at 14.
The Examiner bases this mapping on the following claim
interpretations. Regarding the claimed “last data access address,” the
Examiner interprets “last” as “the most recently occurring access address (in
this case, most recent miss).” Ans. 3. Regarding the claimed “initial missed
data address,” the Examiner interprets “initial” as “a label for a missed data
address occurring before the claimed ‘last data access address.’” Id. The
Examiner elaborates, “a cache miss operation is an access operation that
results in a miss. The claim does not require that the access operation
successfully accesses data without first incurring a miss. Any access
operation that does not hit in the cache will result in a miss.” Id. at 2–3.
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Appellant contends Puzak fails to disclose the limitation at issue
because “[t]he language of claim 21 recites a calculation of a distance
involving a miss and an actual access operation (i.e., not a miss), whereas
Puzak teaches a stride distance between two misses.” App. Br. 5. Appellant
continues, “the Examiner is arguing that the ‘last miss’ corresponds to the
claimed ‘last data access address.’ However, a ‘last miss’ is not a ‘last data
access address,’ as claimed.” Id. at 6. Appellant further asserts, “a teaching
of ‘last’ does not teach or suggest the claimed ‘initial’ (or ‘first’).” Id. at 7;
Reply Br. 7.
We are persuaded by Appellant’s arguments regarding the scope of
independent claim 21. Claim 21 recites, “subtract the last data access
address from the initial missed data address.” App. Br. 12. The
Specification includes the following definition: “The term ‘stride’ as
defined herein may refer to the relative difference between two data
addresses.” Spec. ¶ 38. Consistent with this definition of the stride as the
relative difference between two data addresses, claim 21 more narrowly
recites a stride between two specific types of data addresses, namely a “data
access address” and a “missed data address.” App. Br. 12 (emphasis added).
In light of the plain language of claim 21 and the definition set forth in the
Specification, we agree with Appellant that the claimed “last data access
address” encompasses only data addresses at which data was accessed.
The Examiner fails in the record before us to identify how the cited
teachings of Puzak meet the claim limitation, as construed above, and
therefore, we reverse on that basis the Examiner’s rejection of independent
claim 21 and dependent claims 22–25 and 27. Independent claims 28 and 35
recite commensurate limitations. We reverse the Examiner’s rejections of
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independent claims 28 and 35, and dependent claims 29–32, 34, and 36–39
for the same reasons set forth in the context of independent claim 21.

CONCLUSION
In summary:

Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
21–40 Non-statutory
obviousness type
double patenting.3

21–25, 27–
32, 34–39
103(a) Puzak and
McMinn
21–25, 27–
32, 34–39
Overall
Outcome
21–25, 27–
32, 34–39

REVERSED

3 In light of the terminal disclaimer filed by Appellant, this decision does
not reach the merits of this rejection.