Advanced Micro Devices, Inc.

Patent Trials and Appeals Board

Feb 17, 2022

2021005484 (P.T.A.B. Feb. 17, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/342,809 11/03/2016 Bin He AMD-150254-US-UTL1 1611 25310 7590 02/17/2022 Volpe Koenig DEPT. AMD 30 SOUTH 17TH STREET -18TH FLOOR PHILADELPHIA, PA 19103 EXAMINER PETRANEK, JACOB ANDREW ART UNIT PAPER NUMBER 2183 NOTIFICATION DATE DELIVERY MODE 02/17/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): eoffice@volpe-koenig.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte BIN HE, YUNXIAO ZOU, JIASHENG CHEN, and MICHAEL MANTOR ___________ Appeal 2021-005484 Application 15/342,809 Technology Center 2100 ____________ Before JEAN R. HOMERE, CARL W. WHITEHEAD JR. and BRADLEY W. BAUMEISTER, Administrative Patent Judges. WHITEHEAD JR., Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE1 Appellant2 is appealing the final rejection of claims 1-20 under 35 U.S.C. § 134(a). See Appeal Brief 3. Claims 1, 11 and 20 are 1 Rather than reiterate Appellant’s arguments and the Examiner’s determinations, we refer to the Appeal Brief (filed June 14, 2021), the Reply Brief (filed September 23, 2021), the Final Action (mailed March 4, 2020) and the Answer (mailed July 26, 2021), for the respective details. 2 Appellant refers to “applicant” as defined in 37 C.F.R. 1.42(a). (“The word ‘applicant’ when used in this title refers to the inventor or all of the joint inventors, or to the person applying for a patent as provided in §§ 1.43, 1.45, or 1.46.”). Appellant identifies Advanced Micro Devices, Inc., a company located in Sunnyvale, CA. as the real party in interest. Appeal Brief 3. Appeal 2021-005484 Application 15/342,809 2 independent. An oral hearing was held on February 4, 2022. A transcript of the oral hearing will be entered into the record in due course. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. Introduction According to Appellant: four arithmetic logic units (ALUs) are utilized together to finish one thread’s double precision or transcendental instruction computation. By utilizing dependency between two ALUs instead of four, and utilizing an additional iteration pass, one thread’s transcendental instruction computation can be finished in a fewer number of cycles than conventional schemes. Specification ¶13. Representative Claim3 (disputed limitations emphasized) 1. A method for performing a multi-precision computation in a plurality of arithmetic logic units (ALUs), comprising: pairing a first Single Instruction/Multiple Data (SIMD) block channel device with a second SIMD block channel device to create a first block pair having one-level staggering between the first and second channel devices; 3 Appellant does not argue independent claims 1, 11 and 20 individually. See Appeal Brief 17 (“Claims 11 and 20, although not identical, recite features similar to Applicant’s independent claim 1 and are therefore patentable for at least the same reasons.”). Accordingly, we select independent claim 1 as representative. See 37 C.F.R. § 41.37(c)(1)(iv) (“When multiple claims subject to the same ground of rejection are argued as a group or subgroup by appellant, the Board may select a single claim from the group or subgroup and may decide the appeal as to the ground of rejection with respect to the group or subgroup on the basis of the selected claim alone.”). Appeal 2021-005484 Application 15/342,809 3 pairing a third SIMD block channel device with a fourth SIMD block channel device to create a second block pair having one-level staggering between the third and fourth channel devices; receiving a plurality of source inputs at the first block pair and the second block pair; computing a first result by the first block pair; and computing a second result by the second block pair, wherein the computation of the second result is performed concurrently in a same number of clock time cycles as the computing by the first block pair, and wherein the computations being performed in the first block pair to compute the first result are performed in a same clock time cycle as a corresponding computation being performed in the second block pair. References Name4 Reference Date Sih US 2005/0198472 A1 September 8, 2005 Prokopenko US 2007/0185953 A1 August 9, 2007 Bergland US 8,521,800 B1 August 27, 2013 Veith US 2016/0092237 A1 March 31, 2016 Rejections on Appeal Claims 1, 7 and 20 stand rejected under 35 U.S.C. § 103 as being unpatentable over Bergland, Prokopenko and Sih. Final Action 6-10. Claims 2-6 and 8 stand rejected under 35 U.S.C. § 103 as being unpatentable over Bergland, Prokopenko, Sih and Official Notice. Final Action 10-13. 4 All reference citations are to the first named inventor only. Appeal 2021-005484 Application 15/342,809 4 Claims 9, 10 and 19 stand rejected under 35 U.S.C. § 103 as being unpatentable over Bergland, Prokopenko, Sih and Veith. Final Action 13- 15. Claims 11 and 12 stand rejected under 35 U.S.C. § 103 as being unpatentable over Bergland and Sih. Final Action 2-4. Claims 13-18 stand rejected under 35 U.S.C. § 103 as being unpatentable over Bergland, Sih and Official Notice. Final Action 4-6. ANALYSIS The Examiner finds that, “Bergland, Prokopenko, and Sih disclosed a method for performing a multi-precision computation in a plurality of arithmetic logic units (ALUs).” Final Action 7. The Examiner determines, “[t]he combination of Prokopenko and Bergland allows for the ALU blocks of Bergland to perform SIMD execution via SIMD processing lanes 301-304. The combination implements the pipeline registers of Sih into the ALU blocks of Bergland between the multipliers and adders” wherein the “combination allows for the ADD unit in Bergland to be staggered one-level to receive MUL outputs from other SIMD lanes for execution via the added pipeline registers from Sih.” Final Action 7. The Examiner further determines: The combination with Sih allows for Bergland to concurrently perform two DP2a [two two-dimensional dot products with scalar adds (2 DP2a)] operations over two clock cycles. In the first clock cycle, all ALU block multipliers actively multiply received inputs. In the second clock cycle, all ALU block adders actively add received inputs. Adders 321 and 323 produce each produce a DP2a result.). Final Action 9; see Bergland column 7, lines 17-18. Appeal 2021-005484 Application 15/342,809 5 Appellant contends, “[t]he Bergland reference discloses an arithmetic logic stage in a graphics pipeline including a number of ALUs. The ALUs each include, for example, a multiplier and an adder” wherein the “ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.” Appeal Brief 10 referring to Bergland Figure 3. Appellant further contends that Bergland fails to disclose, teach or suggest the disputed claim limitation recited in claim 1 (“computing a second result by the second block pair . . . compute the first result are performed in a same clock time cycle as a corresponding computation being performed in the second block pair.”). Appeal Brief 12. Appellant argues that Sih does not cure the noted deficiencies of Bergland because “Sih discloses a digital signal processor (DSP) that includes two multiply accumulate (MAC) units and two arithmetic logic units (ALUs), where one of the ALUs replaces an adder for one of the two MAC units” and wherein Sih’s ALUs are not paired as recited in claim 1. Appeal Brief 13 (referring to Sih’s Figure 3), 14. Appellant contends that Prokopenko does not cure the deficiencies of Bergland and Sih because “Prokopenko simply discloses embodiments of a Multiply-Accumulate Unit to process multiple format floating point operands.” Appeal Brief 14 (referring to Prokopenko’s Figure 2A). Appellant argues that, “there is no disclosure, teaching or suggestion in Prokopenko of ‘computing a second result by the second block pair . . . compute the first result are performed in a same clock time cycle as a corresponding computation being performed in the second block pair’”, as is recited in independent claim 1. Appeal Brief 15. Appellant’s arguments are persuasive of Examiner error. As articulated by the Supreme Court, “[R]ejections on obviousness grounds cannot be Appeal 2021-005484 Application 15/342,809 6 sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness.” KSR Int’l., Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) (citing In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)). The Examiner fails to articulate reasoning why the references should be combined in the manner proposed by the Examiner. See Final Action 7, 9. Neither Bergland, Sih nor Prokopenko either alone or in combination discloses pairing block channel devices as required in independent claim 1. Further, as noted above, the Bergland, Sih and Prokopenko combination fails to disclose computing a first and subsequent second result by the first and second block pairs as required in claim 1. Accordingly, we reverse the Examiner’s obviousness rejections of independent claims 1, 11 and 20, commensurate in scope, as well as, dependent claims 2-10 and 12-19. CONCLUSION Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 7, 20 103 Bergland, Prokopenko, Sih 1, 7, 20 2-6, 8 103 Bergland, Prokopenko, Sih, Official Notice 2-6, 8 9, 10, 19 103 Bergland, Prokopenko, Sih, Veith 9, 10, 19 11, 12 103 Bergland, Sih 11, 12 13-18 103 Bergland, Sih, Official Notice 13-18 Appeal 2021-005484 Application 15/342,809 7 Overall Outcome 1-20 REVERSED