Advanced Micro Devices, Inc.

Patent Trials and Appeals Board

Feb 17, 2022

2021005235 (P.T.A.B. Feb. 17, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 16/126,504 09/10/2018 Stanley Ames Lackey JR. AMD-180178-US-ORG1 2203 25310 7590 02/17/2022 Volpe Koenig DEPT. AMD 30 SOUTH 17TH STREET -18TH FLOOR PHILADELPHIA, PA 19103 EXAMINER PETRANEK, JACOB ANDREW ART UNIT PAPER NUMBER 2183 NOTIFICATION DATE DELIVERY MODE 02/17/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): eoffice@volpe-koenig.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte STANLEY AMES LACKEY JR. Appeal 2021-005235 Application 16/126,504 Technology Center 2100 Before JEAN R. HOMERE, CARL W. WHITEHEAD JR., and BRADLEY W. BAUMEISTER, Administrative Patent Judges. HOMERE, Administrative Patent Judge. DECISION ON APPEAL I. STATEMENT OF THE CASE1 Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the Examiner’s decision to reject claims 1-20. Claims App. We have jurisdiction under 35 U.S.C. § 6(b). An oral hearing was held in this appeal on February 4, 2022. A transcript of the oral hearing will be entered into the record in due course. We reverse. 1 We refer to the Specification, filed Sep. 10, 2018 (“Spec.”); Final Office Action, mailed June 17, 2020 (“Final Act.”); Appeal Brief, filed April 1, 2021 (“Appeal Br.”); Examiner’s Answer, mailed July 8, 2021 (“Ans.”); and Reply Brief, filed September 8, 2021 (“Reply Br.”). 2 “Appellant” refers to “Applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Advanced Micro Devices, Inc., Appeal Br. 3. Appeal 2021-005235 Application 16/126,504 2 II. CLAIMED SUBJECT MATTER According to Appellant, the claimed subject matter relates to a method and system for executing requested atomic operations in a large- scale distributed computing network. Spec. ¶ 8. In particular, atomic commands received from off the shelf components 104 at local computer system 101 are translated by translation unit 110 into a format recognizable by processing device 122 in distributed computing unit 120 for subsequent processing. Spec. ¶ 10. Figure 1, reproduced below, are useful for understanding the claimed subject matter: Appeal 2021-005235 Application 16/126,504 3 Figure 1 above depicts distributed computing system 100 including local computer system 101 from which off-the-shelf device 104 issues an atomic request containing an opcode and one or more operands, which translation unit 110 stores within window 112 and translates into a suitable format for subsequent execution by processing device 122 within distributed computing network 120. Spec. ¶¶ 9-14. Claims 1, 10, and 18 are independent. Claim 1, with disputed limitations emphasized, is illustrative: 1. A method for requesting execution of an atomic memory command by a distributed computing network at the request of a processing core, the method comprising: obtaining a free window of a translation unit, the free window comprising a portion of memory of the translation unit; writing an opcode and one or more operands for the atomic memory command into the window; requesting the translation unit to generate the atomic memory command based on contents of the window; and generating the atomic memory command from the contents of the window, the atomic memory command being in a format appropriate for the distributed computing network. Appeal Br. 22 (emphasis added). III. REFERENCES The Examiner relies upon the following references as evidence.3 Name Reference Date Liu US 2009/0271513 A1 Oct. 29, 2009 Guim Bernat US 2018/0004687 A1 Jan. 4, 2018 Laughton US 2019/0179783 A1 June 13, 2019 3 All reference citations are to the first named inventor only. Appeal 2021-005235 Application 16/126,504 4 IV. REJECTIONS The Examiner rejects claims 1-20 as follows: Claims 1, 3-8, 10, 12-16, 18, and 19 stand rejected under 35 U.S.C. § 103 as unpatentable over the combined teachings of Laughton, Liu, and Guim Bernat. Final Act. 2-8. Claims 2, 9, 11, 17, and 20 stand rejected under 35 U.S.C. § 103 as unpatentable over the combined teachings of Laughton, Liu, Guim Bernat, and Official Notice Id. at 8-10. V. ANALYSIS Appellant argues that the Examiner errs in finding that the combined teachings of Laughton, Liu, and Guim Bernat render claim 1 obvious. Appeal Br. 10-14. In particular, Appellant argues that the proposed combination of references does not teach or suggest writing an opcode and one or more operands into a window and generating an atomic memory command based on the contents of that window, as recited in independent claim 1. Id. at 11. According to Appellant, although Laughton discloses a write tracker response buffer, the disclosed buffer is not described as storing both an opcode and operands for atomic memory command. Id. at 11-12 (citing Laughton ¶¶ 65, 66). More particularly, Appellant argues that the disclosed buffer merely stores entries allocated by the request encoder to track write requests received over the write channel; however, no atomic requests are created from the entries stored in the buffer. Id. at 12. Further, Appellant argues that because Liu’s disclosure is solely concerned with data transfer over a packetized network has nothing to do with atomic memory requests, it does not cure the noted deficiencies of Laughton. Id. Appeal 2021-005235 Application 16/126,504 5 In response, the Examiner finds the combined disclosures of Laughton and Liu teach or suggest the disputed limitations. Final Act. Ans. 4. In particular, the Examiner finds the following: [O]btaining a free window of a translation unit, the free window comprising a portion of memory of the translation unit (Liu: Figure 1 elements 118 and 122, paragraphs 15 and 21)(Laughton: Figure 7 elements 92, 98, 114, and 116, paragraphs 64-66 and 68)(The broadest reasonable interpretation of a free window in view of the specification is a portion of memory (see paragraph 16). Laughton disclosed a routing circuit that receives atomic read and write requests at the encoder circuits. Liu disclosed input and output buffers for packetisers to hold pending requests. The combination results in implementing an input and output buffer in Laughton for each of the packetisers. The input buffer entry storing an atomic read or write request reads upon the free window.); writing an opcode and one or more operands for the atomic memory command into the window (Liu: Figure 1 elements 118 and 122, paragraphs 15 and 21)(Laughton: Figure 7 elements 80-84, 92, 98, 114, and 116, paragraphs 64-66 and 68)(Laughton disclosed a routing circuit that receives atomic read and write requests at the encoder circuits. Liu disclosed input and output buffers for packetisers to hold pending requests. The combination results in implementing an input and output buffer in Laughton for each of the packetisers. The input channels to the routing circuit receive the atomic instructions, target addresses, and write data. The buffered requests include the atomic type (i.e. opcode), target address, and/or target data.); Final Act. 3. [T]he combination reads upon the claimed limitation at issue by adding input buffer element 122 from Liu into figure 7 of Laughton between elements 92 and 98, as well as between elements 114 and 116, to buffer requests from Nodes. Ans. 4. We are persuaded by Appellant’s arguments. Appeal 2021-005235 Application 16/126,504 6 Laughton discloses routing circuitry 400 for routing transaction requests and responses between source nodes 50 and destination nodes 52. In particular, upon receiving from requesting node 50 a write request or an atomic request specifying the target address over a write channel, request encoder 92 allocates an entry in the write tracker/response buffer (90) containing buffer entries or slots for storing traffic information for a corresponding write request or atomic request and buffering corresponding write responses. Laughton ¶¶ 64, 65. That is, for each received write request, request encoder 92 creates a tracking entry, which is stored in buffer 90 along with any responses associated therewith. Id. Subsequently, data packetizer 98 is utilized to translate the request into a protocol used by selected destination node 52. Laughton ¶¶ 66. Further, Liu discloses a communication system for adaptively transferring data over a packet network including packetizer 118 for inputting data from input buffer 122, preparing data transmission, and outputting the prepared data to output buffer 124. Liu ¶¶ 15, 21. We agree with Appellant that the combined teachings of Laughton and Liu, as proposed by the Examiner, would not result in writing an opcode and operands into a window for an atomic memory command. Reply Br. 5- 6. More particularly, inserting Liu’s input buffer 122 between Laughton’s request encoder 92 and data packetizer 98 would yield, at best, in request encoder 92 inputting tracking data entries into additional buffer 122 before data packetizer 98 can translate the received write requests or atomic requests. Although the cited portions of Liu indicate that packetizer 118 inputs receives data into input buffer 122, prepares the data, and outputs it into output buffer 124, we note the Examiner’s rejection does not propose to Appeal 2021-005235 Application 16/126,504 7 substitute Liu’s packetizer 118 for Laughton’s packetizer 98, nor does it propose to combine the two. Instead, as noted above, the Examiner’s rejection simply proposes to insert Liu’s input buffer 122 between Laughton’s request encoder 92 and data packetizer 98. Therefore, we do not agree with the Examiner that the proposed insertion of Liu’s input buffer 122 would cause it to buffer requests received from source nodes 50 because such operation of input buffer 122 is dictated by Liu’s packetizer 118, which is omitted from the rejection. That is, in the absence of Liu’s packetizer 118, input buffer 122 would simply be under the control of Laughton’s request encoder 92, which would merely store tracking data (does not include an opcode and one or more operands) in buffers 90 and 122.4 Accordingly, we are persuaded that the cited portions of Laughton and Liu do not teach or suggest the disputed limitations. Because Appellant shows at least one reversible error in the Examiner’s obviousness rejection of independent claim 1, we do not reach Appellant’s remaining arguments. Accordingly, we do not sustain the Examiner’s obviousness rejection of independent claim 1 obvious over the combination of Laughton, Liu, and Guim Bernat. Similarly, we do not sustain the rejections of claims 2-20, which also recite the disputed limitations. 4 We note in passing that additionally combining the functionality of Liu’s packetizer 118 with Laughton’s would result in packetizer 98 /118 that, upon receiving from source node 50 a write request or an atomic request (including an opcode and one or more operands), stores the received request in input buffer 122 where the content thereof is used for translation into a suitable protocol for transmission to destination node 52 via output buffer 124. Appeal 2021-005235 Application 16/126,504 8 VI. CONCLUSION We reverse the Examiner’s rejections of claims 1-20. VII. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 3-8, 10, 12-16, 18, 19 103 Laughton, Liu, Guim Bernat 1, 3-8, 10, 12-16, 18, 19 2, 9, 11, 17, 20 103 Laughton, Liu, Guim Bernat, Official Notice 2, 9, 11, 17, 20 Overall Outcome 1-20 REVERSED