Advanced Micro Devices, Inc.

Patent Trials and Appeals Board

Jun 3, 2021

2020001430 (P.T.A.B. Jun. 3, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/672,722 03/30/2015 Greg Sadowski 1458-0540 9892
102347 7590 06/03/2021
Polansky & Associates, P.L.L.C.
12600 Hill Country Blvd
Suite R-275
Austin, TX 78738
EXAMINER
LEWIS-TAYLOR, DAYTON A.
ART UNIT PAPER NUMBER
2181
NOTIFICATION DATE DELIVERY MODE
06/03/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
admin@patentwerks.net
ppolansky@patentwerks.net
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte GREG SADOWSKI and JOHN KALAMATIANOS,
____________________

Appeal 2020-001430
Application 14/672,722
Technology Center 2100
____________________

Before JOHN A. JEFFERY, ST. JOHN COURTENAY III, and
JOHNNY A. KUMAR, Administrative Patent Judges.

KUMAR, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
final rejection of claims 1, 2, 4, 6–8, 10–20.2 We have jurisdiction under
35 U.S.C. § 6(b).

We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. According to Appellant, Advanced Micro Device, Inc. is
the real party in interest. Appeal Br. 3.
2 Claims 3, 9, 21–23 are canceled. Appeal Br. 3. Claim 5 has been allowed.
Final Act. 11.
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STATEMENT OF THE CASE
Appellant’s invention relates to a method of reducing dynamic power
consumption in a bus interconnect when data is being transmitted over the
bus interconnect. See Spec. ¶ 13.3 The method includes configuring a
buffer array to store data in a plurality of rows and columns. Id. The data
stored in the buffer array is analyzed to determine a mode of transmitting
data that uses the least amount of power. See Id. The determined mode is
then used to transmit the data. Id.
Claims 1 and 4, reproduced below, are representative of the subject
matter on appeal (emphasis, formatting, and bracketed material added):

1. A method of reducing power consumption in a bus
interconnect comprising:

receiving a dataword having a
predetermined number of bits;
[L1]storing data of the dataword in a
plurality of rows and a plurality of columns of a
two dimensional (2D) buffer array, wherein each
of the plurality of rows and the plurality of
columns is greater than two in number;
[L2] analyzing the data stored in the 2D
buffer array for transmission over the bus
interconnect to determine a mode of a plurality of
modes of transmitting the stored data, [L3] the
determined mode being a mode using a least
amount of power to transmit the dataword; and
transmitting the stored data of the dataword
over the bus interconnect according to the
determined mode until all the data in the 2D buffer
array is transmitted, in a plurality of transmission
cycles.

3 We refer to Appellant’s Published Specification, Application No. US
20160291678A1 published on October 6, 2016.
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4. The method of Claim 1, [L4] wherein the stored data is
further encoded using an encoding algorithm.

Appeal Br. 21, 22 (Claims Appendix)

Evidence
The prior art relied upon by the Examiner as evidence is:
Name Reference Date
Chang US 6,385,122 B1 May 7, 2002
Hollis US 2009/0313521 A1 Dec. 17, 2009
Pekonen et al. US 2005/0013275 A1 Jan. 20, 2005

The rejections before us on appeal are:

Claims
Rejected
35 U.S.C. § Reference(s)/Basis
1–2, 6–8,
12–20
103 Chang, Hollis, Pekonen
4, 10–11 103 Chang, Hollis, Pekonen

ANALYSIS
In reaching this Decision, we consider all evidence presented and all
arguments actually made by Appellant. We have reviewed Appellant’s
arguments in the Appeal Brief, the Examiner’s rejections in the Final Office
Action, and the Examiner’s responses in the Answer to Appellant’s
arguments. We highlight and address specific findings and arguments for
emphasis as follows: 4

4 Throughout this Decision, we refer to the Reply Brief filed December 16,
2019 (“Reply Br.”); the Appeal Brief filed July 24, 2019 (“Appeal Br.”);
Final Office Action mailed February 25, 2019 (“Final Act.”); and the
Examiner’s Answer mailed November 21, 2019 (“Ans.”).
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35 U.S.C. § 103 Rejection of Exemplary Claim 1
We have reviewed the Examiner’s rejections in light of Appellant’s
contentions that the Examiner has erred. See Appeal Br. 7–25; Reply Br. 2–
4.
A. Claim 1, Limitation L1
We first consider the claim construction under BRI (broadest
reasonable interpretation) of the disputed claim term “dataword.” We turn
to the Specification for context, and find the Specification provides a non-
limiting, exemplary description for the claim term “dataword”:
In this Figure, dataword 402 represents data from a transmitting
device. Specifically, data from a transmitting device may be
divided in chunks large enough to fit in rows and/or columns of
N×N buffer array 410. In this case, since N is eight (8), an 8-bit
dataword is used (i.e., 8-bit chunks of data are used).

Spec. ¶ 31 (emphases added).
Each dataword 402 from the transmitting device is written into a
column of N×N data array 410.

Spec. ¶ 32 (emphases added).
Thus, “dataword” can be “data large enough to fit in rows and/or
columns of N×N buffer array.” Spec. ¶¶ 31–32.
The Examiner concludes the term “word” refers to data of 8-bits and
finds that Chang’s “word,” “COL_WORDs” and “ROW_WORDS” teaches
or suggests the claimed dataword. Final Act. 3.
Chang teaches:
Similar to the conventional column accessible memory circuit
shown in FIG. 2, reference numerals 520_0 through 520_(N-1)
refer to N column or vertical words (COL_WORDs) and
reference numerals 518_0 through 518 (N-1) refer to N row or
horizontal words (ROW_WORDs).
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Final Act. 3 (citing Chang col 7, ll: 50-55) (emphases added).
Appellant argues that Chang does not teach limitation L1 because
Chang’s 8-bit dataword would not meet with the requirements of a
“dataword” of the claim 1. Appeal Br. at 13. Appellant argues that Chang’s
8 bit word does not teach dataword because claim 1 (limitation L1) requires
the “dataword” to be stored in a 2D array in a plurality of rows greater in
number than two and a plurality of columns greater in number than two. Id.
According to Appellant, the smallest size of the 2D array consistent with the
language of claim 1 would be 3 rows by 3 columns, for a total of 9 bits. Id.
We disagree. As discussed above, Appellant’s Specification describes
“dataword” as an N-bit dataword that fits in each row or each column of an
N×N buffer array. Spec. ¶ 31. Paragraph 32 of Appellant’s Specification
describes storing one dataword in a column of the N×N buffer array. Spec. ¶
32.
Appellant’s argument that a dataword should be of N×N bits in order
to fill up all the rows and columns of N×N buffer array is contrary to
Appellant’s own Specification. We further note that “storing data of the
dataword in a plurality of rows and a plurality of columns of a two
dimensional (2D) buffer array” required by claim 1 is not the same as, nor
does the claim require, using data of the dataword to fill up all of rows and
columns of the two dimension (2D) buffer array suggested by Appellant.
Given the evidence cited by the Examiner, and in accordance with our
claim construction above, we are not persuaded of error regarding the
Examiner’s underlying factual findings that support the ultimate legal
conclusion of obviousness. Accordingly, we are not persuaded that the
Examiner erred in finding that Chang teaches L1.
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B. Claim 1, Limitations L2 and L3
The Examiner finds that the combination of Chang and Hollis teaches
limitations L2 and L3 because Chang teaches either a row access operation
or a column access operation for accessing data stored in a 2D buffer array,
and Hollis teaches a mode using the least amount of power to transmit data
over a bus interconnect. Final Act. 3–4 (citing Chang col 2, ll: 5–38; col 7,
ll: 47–48 and Hollis ¶¶ 2–3).
Appellant argues that Chang does not teach limitation L2 because
Chang does not analyze data. Appeal Br. 14. Appellant argues that Hollis
does not teach limitations L2 and L3 because Hollis does not analyze a
dataword that requires more than two rows and more than two columns for
storage. Id. 15–16. According to Appellant, Hollis analyzes adjacent data
elements two at a time, and determines the mode for the data on an element-
by-data element basis. Id. at 15. Appellant argues that the combination of
Chang and Hollis does not teach limitations L2 and L3 because the DBI
technique disclosed in Hollis would not analyze the data of a dataword in a
2D array in which each of the plurality of rows and the plurality of columns
is greater than two, with a determined mode using the least amount of power
to transmit the dataword. Id. at 17; Reply Br. 3.
Appellant’s arguments with respect to Chang and Hollis do not
address the specific findings made by the Examiner. In particular, the
Examiner finds that the combination of Chang and Hollis, rather than Chang
alone that teaches limitations L2 and L3. See Final Act. 3–4.
We also disagree with Appellant that Hollis does not teach analyzing
the dataword because we note that Fig. 6 of Hollis explicitly teaches
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analyzing an 8 bit DQ’ data and encoding it in an 8-bit data DQ” column of
the buffer array 216. Hollis’s Figure 6 (modified) is reproduced below.

Modified Figure 6 of Hollis illustrates analyzing and encoding 8-bit data

Again, Appellant’s arguments above have ignored the combined
teachings and suggestions of Chang and Hollis. Specifically, we find no
error with the Examiner’s finding that an ordinarily skilled artisan would
have had sufficient motivation to apply the teachings of Chang—to
determine to select either a row access operation for accessing a selected
row or a column access operation for accessing a selected column (see Final
Act. 4)—to the teachings of Hollis—to analyze the data for transmission
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over the bus interconnect to determine a mode using the least amount of
power to transmit the dataword (id. at 4–5).
Accordingly, based upon a preponderance of the evidence before us,
we are not persuaded that the Examiner erred in finding that the combination
of Chang and Hollis teaches or suggests limitations L2 and L3.
C. Reasons for combining Pekonen with Chang and Hollis
Appellant argues the rationale “for the benefit of having provided
systems and methods wherein a two-dimensional array or the like is
employable in data transmission and/or reception” would not have supported
the combination of Pekonen with Chang and Hollis because the reason
offered by the Office is conclusory, and thus improper. Appeal Br. 17.
We agree with the Examiner’s finding that relies on paragraph 12 of
Pekonen for providing a rationale to combine Chang and Hollis. Final Act.
4 (citing Pekonen ¶¶ 12, 47). The above-noted teachings suggest that the
combination involves the predictable use of prior art elements according to
their established functions.
The Supreme Court has held that in analyzing the obviousness of
combining elements, a court need not find specific teachings, but rather may
consider “the background knowledge possessed by a person having ordinary
skill in the art” and “the inferences and creative steps that a person of
ordinary skill in the art would employ.” KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398,418(2007). To be nonobvious, an improvement must be “more
than the predictable use of prior art elements according to their established
functions,” id. at 417, and the basis for an obviousness rejection must
include an “articulated reasoning with some rational underpinning to support
the legal conclusion of obviousness.” Id. at 418 (citation omitted).
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Here, the Examiner has provided a rationale for the combination,
which is to facilitate an employment of a two-dimensional array in data
transmission and/or reception. Final Act. 19 (citing Pekonen ¶¶ 12, 47).
Accordingly, we find that the Examiner has provided sufficient motivation
for combining Chang and Hollis with the teachings of Pekonen.
Moreover, Appellant has not provided persuasive evidence that
combining the respective teachings of the references (as proffered by the
Examiner – Final Act. 4) would have been “uniquely challenging or difficult
for one of ordinary skill in the art,” or that such a combination would have
“represented an unobvious step over the prior art.” Leapfrog Enters., Inc. v.
Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007). Nor has Appellant
provided any objective evidence of secondary considerations, which, as our
reviewing court explains, “operate[] as a beneficial check on hindsight.”
Cheese Systems, Inc. v. Tetra Pak Cheese and Powder Systems, Inc., 725
F.3d 1341, 1352 (Fed. Cir. 2013).
Accordingly, Appellant does not persuade us of error in the
Examiner’s finding that a person having of ordinary skill in the art at the
time of the invention would have combined Pekonen, Chang, and Hollis.
D. Reply Brief
Appellant presents for the first time in the Reply Brief arguments
against the rejection of the claim 1. Reply Br. 3–4. Appellant has not
shown good cause for raising the new arguments, thus we decline to
consider an argument raised for the first time in the Reply Brief, as the
Examiner has not been provided a chance to respond. See 37 C.F.R.
§ 41.41(b)(2) (2018).
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In particular, the Appellant argues that “the Office makes an
unwarranted leap of logic that is not reasonable based on the cited prior art
and the level of ordinary skill in the art” when combining Hollis with Chang
because the “present claims do not require that the mode of transmitting data
involves encoding data at all, …but merely transmits data unencrypted either
row-wise or column-wise transmission depending on which mode would
result in less power.” Reply Br. 3.
Nonetheless, we find the Examiner is appropriately relying on
suggestions and logical inferences as would have been understood by the
ordinarily skilled artisan from Hollis. That is, the Examiner’s conclusion
relies on paragraph 3 of Hollis. Ans. 4 (citing Hollis ¶ 3). Here, the
Examiner has provided a rationale for the combination, which results in a
less amount of power being consumed to perform data transfer. Ans. 4
(citing Hollis ¶ 3). Although the present claims do not require the mode of
transmitting data involving encoding data, they do not preclude encoding
data to transmit data either. See Appeal Br. 21 (claim 1 does not preclude
encoding data). Accordingly, we find that the Examiner has provided
sufficient motivation for combining the teachings of Hollis and Chang.
Accordingly, Appellant does not persuade us of error in the
Examiner’s finding that a person having of ordinary skill in the art at the
time of the invention would have combined Chang and Hollis.
Appellant also for the first time argues that Pekonen does not teach
“the use of a two-dimensional (2D) array that transmits data until all the data
in the 2D buffer array is transmitted” because paragraph 47 of Pekonen
states selecting all or some elements in one row or column, rather than the
whole array. Reply Br. 4.
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The Examiner finds, and we agree, that Pekonen teaches transmitting
data until all the data in the 2D buffer array is transferred because Pekonen
selects all the elements in one row or column to compute the characteristic
values. Final Act. 4 (citing Pekonen ¶ 47). We note that Figure 1 of
Pekonen teaches that the whole array is selected because the characteristic
values is computed with respect to each row of the two-dimensional array.
Figure 1 of Pekonen further discloses the two-dimensional array or the like
could be emptied in a columnar-wise manner in step 105, which maps to
transmit all the data in the 2D buffer array. See Pekonen ¶ 30 (describing
step 105 in Figure 1 of Pekonen). Pekonen’s Figure 1 (modified) is
reproduced below.
Modified Figure 1 of Pekonen illustrates steps in data transmission
Based on this record, Appellant does not persuade us of error in the
Examiner’s rejection of independent claims 1, 6, 18, and claims 2, 5–8, 12–
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17 and 19–20 falling therewith (Appeal Br. 6) over Chang, Hollis, and
Pekonen.

35 U.S.C. § 103 Rejection of Claims 4, 10–11
We have reviewed the Examiner’s rejection of claims 4 and 10 in light
of Appellant’s arguments that the Examiner has erred. In rejecting claims 4
and 10, the Examiner finds Hollis teaches limitation L4 because Hollis uses
Data Bus Inversion (DBI) encoding to encode the data. Final Act. 5 (citing
Hollis Abstract).
The Abstract of Hollis, as relied upon by the Examiner (Final Act. 5),
is reproduced below:
Implementations of Data Bus Inversion (DBI) techniques
within a memory system are disclosed. In one
embodiment, a set of random access memory (RAM)
integrated circuits (ICs) is separated from a logic system
by a bus. The logic system can contain many of the logic
functions traditionally performed on conventional RAM
ICs, and accordingly the RAM ICs can be modified to
not include such logic functions. The logic system, which
can be a logic integrated circuit intervening between the
modified RAM ICs and a traditional memory controller,
additionally contains DBI encoding and decoding
circuitry. In such a system, data is DBI encoded and at
least one DBI bit issued when writing to the modified
RAM ICs. The RAM ICs in turn store the DBI bit(s) with
the encoded data. When the encoded data is read from the
modified RAM ICs, it is transmitted across the bus in its
encoded state along with the DBI bit(s). The logic
integrated circuit then decodes the data using the DBI
bit(s) to return it to its original state.

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Hollis, Abstract (Emphasis added).
Appellant contends that the Examiner erred in rejecting claims 4 and
10 because:
Hollis discloses various implementations of a system
that performs data bus inversion (DBI) as data is being
transmitted to or from memory to use a least amount of
power between adjacent elements data transmitted on the
bus. See Hollis at FIGs. 2B and 5. Thus the “mode using
the least amount of power to transmit the dataword” is
whether to invert each data element or not. Hollis,
however, does not disclose an encoding algorithm that is
used in addition to inversion mode with DBI.
. . . .
Claims 4 and 10 disclose using an additional encoding
algorithm beyond the “mode”recited in in base claims 1
and 6, respectively. For example, claim 4 recites
“wherein the stored data is further encoded using an
encoding algorithm (emphasis added)”. Thus claim 4
recites further encoding the stored data using an encoding
algorithm in addition to the mode selection
based on the determined mode using a least amount of
power to transmit the dataword.
. . . .
The Office did not identify any reason to apply an
encoding algorithm in addition to the mode selection.
Thus the Office failed to articular any reason why an
extra encoding algorithm would have been obvious in
view of the combination of Chang, Hollis, and Pekonen,
or provide a reason it would have been otherwise obvious
to one of ordinary skill in the art.

Appeal Br. 19 (Emphases added).

Appellant provides support for the argument with Figure 5 of Hollis,
which is also reproduced below.
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Modified Figure 5 of Hollis illustrates DBI encoding included on a
logic integrated circuit
As articulated by the Federal Circuit, the Examiner’s burden of
proving non-patentability is by a preponderance of the evidence. See In re
Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985) (“[P]reponderance of the
evidence is the standard that must be met by the PTO in making rejections”).
“A rejection based on section 103 clearly must rest on a factual basis[.]” In
re Warner, 379 F.2d 1011, 1017 (CCPA 1967). “The Patent Office has the
initial duty of supplying the factual basis for its rejection. It may not . . .
resort to speculation, unfounded assumptions or hindsight reconstruction to
supply deficiencies in its factual basis.” Id. We conclude the Examiner’s
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analysis fails to meet this standard because the rejection does not adequately
explain the Examiner’s findings of fact.
Appellant’s contentions on page 19 of the Reply Brief are persuasive.
We concur with Appellant’s assertion that the Examiner erred in finding that
Hollis teaches limitation L4 as recited in claim 4, and similarly recited in
claim 10. Specifically, we agree with Appellant that claim 4 recites further
encoding the stored data using an encoding algorithm in addition to the
mode selection based on the determined mode using a least amount of power
to transmit the dataword. Appeal Br. 19. In addition, we agree with
Appellant that the cited portions of Hollis does not disclose an encoding
algorithm in addition to inversion mode with DBI. Id.
On this record, the Examiner has not sufficiently shown (Ans. 4–5),
nor do we find, that Hollis teaches limitation L4, as required by the claim.
We conclude, consistent with Appellant’s arguments, that there is currently
insufficient articulated reasoning to support the Examiner’s finding and legal
conclusion that Hollis teaches, suggests, or otherwise renders obvious
limitation L4, as required by claims 4 and 10.
Because we have reversed the rejection for claims 4 and 10, we also
reverse the Examiner’s rejection of claim 11 for the same reasons because
claim 11 depends on claim 10.

CONCLUSION

The Examiner did not err in rejecting claims 1–2, 6–8, 12–20 under
35 U.S.C. § 103 over the combined teachings and suggestions of the cited
references.
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The Examiner erred with respect to the rejection of claims 4, 10–11
under 35 U.S.C. § 103 over the combined teachings and suggestions of the
cited references.

DECISION SUMMARY

In summary:

Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–2, 6–8,
12–20
103 Chang, Hollis,
Pekonen
1–2, 6–8,
12–20

4, 10–11 103 Chang, Hollis,
Pekonen
4, 10–11
Overall
Outcome
1–2, 6–8,
12–20
4, 10–11

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED IN PART