Opinion
Civil Action No. 10-cv-03013-PAB-KLM
08-16-2012
BIAX CORPORATION, Plaintiff, v. MOTOROLA SOLUTIONS, INC., et al., Defendants.
Judge Philip A. Brimmer
ORDER
This matter is before the Court for the construction of U.S. Patent No. 5,517,628 (the "'628 Patent") [Docket No. 225-2] and U.S. Patent No. 6,253,313 (the "'313 Patent") [Docket No. 225-11] (collectively, the "patents"), both assigned to plaintiff BIAX Corporation ("BIAX"). BIAX alleges that defendants have infringed the patents. The parties ask the Court to construe certain disputed terms in the patents. The Court held a status conference on March 8, 2012, during which it decided to limit claim construction, at least at this stage of the litigations, to three terms: "condition code register," "condition storage," and "registers for storage of intermediate results of instructions executed by said processors." On March 15, 2012, the Court held a hearing pursuant to Markman v. Westview Instruments, Inc., 517 U.S. 370 (1996) on these terms.
I. BACKGROUND
The '628 Patent and the '313 Patent share the same specification, as both patents derive from U.S. Patent No. 4,847,755. The invention described in both patents "generally relates to parallel processor computer systems and, more particularly, to parallel processor computer systems having software for detecting natural concurrencies in instruction streams and having a plurality of processor elements for processing the detected natural concurrencies." '313 Patent col. 1 ll. 18-23.
The patents describe both software and hardware. The software, which is referred to as "TOLL" software, is capable of identifying "natural concurrencies" in instructions and assigning hardware components, including processor elements, accordingly. The invention describes processor elements that access register files containing information required for subsequent processing of instructions. More specifically, the invention includes condition code register files containing multiple, addressable condition code registers, each of which may hold condition codes indicating whether the results of executed instructions meet certain conditions. The condition codes can include indications of whether the next instruction in a series should be executed or whether a branch must be taken, requiring a jump to an earlier or later instruction.
The "condition code register" and "condition storage" are introduced in Claim 1 of each patent, and the term "registers for storage of intermediate results of instructions executed by said processors" appears in Claim 18 of the '628 Patent.
Claim 1 of the '628 Patent describes:
A computer comprising:
a general purpose register file comprising at least two general purpose registers;'628 Patent col. 45 l. 63 - col. 46 l. 28.
a condition code register file distinct from said general purpose register file, having a plurality of addressable condition code registers, each condition code register for representing a condition code value as a small number of bits summarizing the execution or result of a previously-executed instruction;
a processor element configured to execute instructions, including condition-setting instructions that each produce a condition code value for storage in one of said condition code registers;
a branch execution unit configured to execute conditional branch instructions that each determine a target instruction for execution based on analysis of a condition code value from one of said condition code registers; and
a condition code access unit configured to act in response to condition-selecting instructions, at least one of said condition-selecting instructions being one of either said condition-setting instructions or said conditional branch instructions, said condition-selecting instructions for selecting from said condition code register file a condition code register for at least one of:
storing into said selected condition code register a condition code value produced by one of said condition-setting instructions, and
fetching from said selected condition code register a condition code value for analysis by one of said conditional branch instructions;
said selecting being by direct addressing on a condition code address field of the condition-selecting instruction.
Claim 18 of the '628 Patent reads as follows:
A computer comprising:'628 Patent col. 48 ll. 31-53.
at least two processors, each relying on a common shared register file of at least two registers for storage of intermediate results of instructions executed by said processors, registers of said shared register file being directly address by register selection fields of said instructions;
an interconnect between said processors and said register file configured to:
store into a register of said shared register file a summary of a condition of the result of a condition-setting one of said instructions executed by a first of said processors, and
deliver said condition summary from said register to a second of said processors for analysis in determining the branch target of a conditional branch instruction of said instructions executed on said second processor;
said register selected from within said register file by a condition code address field of said condition-setting instruction, and said register selected from within said register file by a condition code address field of said conditional branch instruction.
Claim 1 of the '313 Patent provides for the following:
A parallel processor system for processing natural concurrencies in streams of low level instructions contained in a plurality of programs in said system, each of said streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system comprising:'313 Patent col. 45 l. 35 - col. 46 l. 24.
means (160) for statically adding intelligence to each instruction in each of said plurality of basic blocks for each said program, said added intelligence at least having a logical processor number (LPN) and an instruction firing time (IFT)
a plurality of contexts (660), each of said contexts being assigned to one of said plurality of programs for processing one of said programs, each of said contexts having at least a plurality of registers and a plurality of condition code storages for containing processing status information,
a plurality of logical resource drivers (LRDs) with each logical resource driver being assigned to on[e] []of said plurality of contexts, each of said logical resource drivers being receptive of said basic blocks corresponding to the program instruction stream of said assigned program from said adding means, each of said logical resource drivers comprising:
(a) a plurality of queues (1560), and
(b) means (630, 6200 operative on said plurality of said basic blocks containing said intelligence from said adding means for delivering said instruction[s] []in each said basic block into said plurality of queues based on said logical processor number, said instruction[s] []in each said queue being entered according to said instruction firing time
wherein the earliest instruction firing time is entered first,a plurality of individual processor elements (PEs), each of said processor elements being free of any context information,
means (650) connecting said plurality of processor elements to said plurality of logical resource drivers for transferring said instructions with the earliest instruction firing time first in said queues from each of said logical resource drivers, in a predetermined order, to individually assigned processor elements, each said processor element being capable of processing said transferred instruction,
first means (670) for connecting each of said processor elements with any one of said plurality of contexts, each of said processor elements being capable of accessing said plurality of registers and condition code storages in a program's context during the processing of the program's instruction,
a plurality of memory locations (610), and
second means (620, 630) for connecting each of said processor elements with any one of said plurality of memory locations, each said processor element being capable of accessing said memory locations during said processing of each said instruction.
Before addressing the three terms referred to earlier, the Court will discuss the legal standards applicable to claim construction.
II. LEGAL STANDARDS FOR PATENT CLAIM CONSTRUCTION
Claim construction is a question of law for the court, see Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1454 (Fed. Cir. 1998) (en banc), guided by Federal Circuit precedent. See SunTiger, Inc. v. Scientific Research Funding Group, 189 F.3d 1327, 1333 (Fed. Cir. 1999). The Federal Circuit has made clear that "there is no magic formula or catechism for conducting claim construction." Phillips v. AWH Corp., 415 F.3d 1303, 1324 (Fed. Cir. 2005) (en banc). Nevertheless, there are several key sources and doctrines that should be consulted and applied, but "[t]he sequence of steps used by the judge in consulting various sources is not important; what matters is for the court to attach the appropriate weight to be assigned to those sources in light of the statutes and policies that inform patent law." Id.
The starting point is the "bedrock principle" that "'the claims of the patent define the invention to which the patentee is entitled the right to exclude.'" Id. at 1312 (quoting Innova/Pure Water, Inc. v. Safari Water Filtration Systems, Inc., 381 F.3d 1111, 1115 (Fed. Cir. 2004)). The words of the claims "'are generally given their ordinary and customary meaning,'" id. (quoting Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)), which is "the meaning that the term would have to a person of ordinary skill in the art in question at the time of the invention," id. at 1313; see CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002) ("Generally speaking, [courts] indulge a 'heavy presumption' that a claim term carries its ordinary and customary meaning."). In those instances when the claim language "involves little more than the application of the widely accepted meaning of commonly understood words," construction is relatively straightforward and "the ordinary meaning . . . may be readily apparent even to lay judges." Phillips, 415 F.3d at 1314. When the claim terms have a particular meaning in the field, however, courts "look[ ] to 'those sources available to the public that show what a person of skill in the art would have understood disputed claim language to mean.'" Id. (quoting Innova, 381 F.3d at 1116). These sources include "'the words of the claims themselves, the remainder of the specification, the prosecution history, and extrinsic evidence concerning relevant scientific principles, the meaning of technical terms, and the state of the art.'" Id.
The context in which a term is used, both in the asserted claim as well as in other claims of the patent, can be valuable and instructive. Id. at 1314. In addition, the patent specification - the text and figures of the patent that precede the claims - "'is always highly relevant to the claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of a disputed term.'" Id. at 1315 (quoting Vitronics, 90 F.3d at 1582). With that said, "the claim requirement presupposes that a patent applicant defines his invention in the claims, not in the specification." Johnson & Johnston Associates Inc. v. R.E. Service Co., Inc., 285 F.3d 1046, 1052 (Fed. Cir. 2002); see PSC Computer Products, Inc. v. Foxconn Intern., Inc., 355 F.3d 1353, 1359 (Fed. Cir. 2004) ("'[T]he claims of a patent limit the invention, and specifications cannot be utilized to expand the patent monopoly[.]'") (quoting United States v. Adams, 383 U.S. 39, 48-49 (1966)).
If necessary, courts may also consider the patent's prosecution history - the official record of the patent application and subsequent process before the U.S. Patent and Trademark Office, which "provides evidence of how the PTO and the inventor understood the patent." Phillips, 415 F.3d at 1317. Nevertheless, "because the prosecution history represents an ongoing negotiation between the PTO and the applicant, . . . it often lacks the clarity of the specification and thus is less useful for claim construction purposes." Id. And, although courts may consult extrinsic evidence such as "expert and inventor testimony, dictionaries, and learned treatises," such evidence is "'less significant than the intrinsic record,'" i.e., the specification and prosecution history, and courts must be wary not to use extrinsic evidence to override the meaning of the claim terms demonstrated by the intrinsic evidence. Id. at 1317-19 (quoting C.R. Bard, Inc. v. U.S. Surgical Corp., 388 F.3d 858, 862 (Fed. Cir. 2004)). That is, "extrinsic evidence may be useful to the court, but it is unlikely to result in a reliable interpretation of patent claim scope unless considered in the context of the intrinsic evidence." Id. at 1319.
In short, a court must construe the claim terms as they would be viewed by "the ordinary artisan after reading the entire patent." Id. at 1321. This is crucial in order to respect the public notice function of patents:
The patent system is based on the proposition that claims cover only the invented subject matter. As the Supreme Court has stated, "[i]t seems to us that nothing can be more just and fair, both to the patentee and the public, than that the former should understand, and correctly describe, just what he has invented, and for what he claims a patent."Id. at 1321 (quoting Merrill v. Yeomans, 94 U.S. 568, 573-74 (1876)).
III. ANALYSIS
The Court now turns to construing the terms "condition code storage," "condition storage," and "registers for storage of intermediate results of instructions executed by said processors." The parties agree that the definition for "condition code register" should include the following: "special purpose register for storing a condition code." Docket No. 226 at 19. The parties also agree that "condition storage" is a "memory location designed to store condition code values." Id. Defendants, however, request that the Court add the following to each definition: "any processor element is able to access any condition code register" or "condition storage." Docket No. 225 at 16. The dispute, therefore, turns on the inclusion of language referring to shared access by processor elements to the "condition code register" and "condition storage."
Claim 1 of the '628 Patent provides for "a general purpose register file comprising at least two general purpose registers" and "a condition code register file distinct from said general purpose register file, having a plurality of addressable condition code registers, each condition code register for representing a condition code value as a small number of bits summarizing the execution or result of a previously-executed instruction." '628 Patent col. 45 l. 64 - col. 46 l. 4. Claim 1 further describes a "processor element configured to execute instructions, including condition-setting instructions that each produce a condition code value for storage in one of said condition code registers." '628 Patent col. 46 ll. 5-8. Then, upon introduction of "at least one additional processor element," the "condition code register file [is] shared by said processor elements." '628 Patent col. 46 ll. 30, 37-39 (Claim 2).
The parties' dispute regarding the proper construction of "condition code register" is less a matter of what that term means than what the claim reveals about shared access to condition code registers. Although BIAX rejects defendants' suggestion to include reference to shared access by processor elements in the definitions, it does not dispute that the patents "provide[] for shared access to condition code registers upon the introduction of additional processor elements." Docket No. 226 at 21; cf. '628 Patent col. 14 ll. 53-54 ("[A]ny processor element . . . can access any register file or condition code storage in any context."). BIAX also admits that, in the event there is only one processor element, that processor element is capable of accessing any of the "condition code registers." BIAX, however, believes that because this capability of processor elements is described by the aforementioned claim language, it is unnecessary to import that quality into the definition of "condition code registers." See Docket No. 226 at 21. The Court agrees.
At the March 15, 2012 claim construction hearing, counsel for BIAX reiterated that any processor element can access every condition code register. Cf. '628 Patent col. 16 ll. 27-33 ("Under the teachings of the present invention, each processor element . . . is 'totally coupled' to the necessary registers in the register file . . . during any particular instruction firing time . . . . and, therefore, there is no need to move the data out of the register file for delivery to another resource; e.g. in another processor's register as in some conventional approaches.").
The Court concludes that the shared access is more directly related to the appropriate definition of "processor element" (a term the parties have not disputed in this matter) than to "condition code register." This Court construed "processor element" in BIAX v. NVIDIA, et al., No. 09-cv-01257-PAB-MEH, 2010 WL 2539769 (D. Colo. June 21, 2010), concluding that it is a "device that is capable of interpreting and executing instructions, a quality it shares with all other processor elements, and which does not retain context information after the execution of an instruction or a set of instructions." Id. at *11. Rather than retaining such information, the processor element, upon execution of an instruction or set of instructions, is able to access the "condition code registers" in order to store and retrieve condition code values. See '628 Patent col. 46 ll. 5-8; cf. id. col. 16 ll. 18-21 ("[W]hen a particular processor element . . . places results of its operation in a register, any processor element . . . can be interconnected to that register as it executes its operation."); id. col. 16 ll. 41-43 ("[A]ny processor element has full access to any configuration of registers . . . as if such registers were its own internal registers."). The Court sees no reason to also incorporate this requirement into the definition of "condition code register." Defendants fail to offer a persuasive reason to do so; instead, they express their concern that, despite the foregoing, BIAX may later argue that "condition code registers" are not accessible to all processor elements. However, not only has BIAX not disputed that they are, but to incorporate that fact into the definition of "condition code register" would duplicate what the claim language already provides and would serve no purpose other than emphasis. The Court concludes, therefore, that "condition code register" means "special purpose register for storing a condition code."
In regard to "condition storage," the Court also believes it unnecessary to incorporate the processor elements' shared access into the term's definition. Claim 1 of the '313 Patent clearly describes the sharing of "condition storage" by processor elements. See '313 Patent col. 46 ll. 14-24 (". . . each of said processor elements being capable of accessing said plurality of registers and condition code storages in a program's context during the processing of the program's instruction, a plurality of memory locations . . ., and second means . . . for connecting each of said processor elements with any one of said plurality of memory locations, each said processor element being capable of accessing said memory locations during said processing of each said instruction."). As BIAX correctly pointed out during the March 15, 2012 claim construction hearing, the language of the claims makes clear that the first and second circuit share the condition code storage. The Court fails to see why this language requires repeating through incorporation into the meaning of "condition storage." Consequently, the Court construes the term "condition storage" to mean a "memory location designed to store condition code values."
Finally, in regard to "registers for storage of intermediate results of instructions executed by said processors," language that appears in Claim 18 of the '628 Patent, BIAX suggests "registers for storage of condition code values," while defendants believe it should be construed in the same manner as "condition code register." BIAX, however, does not offer any separate argument regarding this claim term and does not refute defendants' contention that the dispute also turns on the "requirement of shared access specified in the latter portion of Defendants' construction." Docket No. 225 at 21. Claim 18 describes the shared access of "at least two processors" to these "registers for storage of intermediate results of instructions executed by said processors." '628 Patent col. 48 ll. 31-34. The Court again fails to discern why this description, which appears in the claim, must be repeated in the definition of the term. Moreover, the Court declines to further construe the term as the parties do not explain what aspect of the term is unclear or requires further explanation. To the extent the registers serve a special purpose, that purpose appears to be clearly described by the language of the term itself, i.e., that its purpose is "for storage of intermediate results of instructions." The parties do not explain their respective views on the distinction between "condition code values" or "condition codes" and these "intermediate results," which Claim 18 appears to describe as a "condition summary." '628 Patent col. 48 ll. 41, 44. Because the parties have not argued that any such distinction is material, the Court will not address it at this time.
IV. CONCLUSION
Accordingly, the patent claim terms presently at issue shall be construed as follows:
• Condition Code Register: a special purpose register for storing a condition code
• Condition Storage: a memory location designed to store condition code values
• Registers for Storage of Intermediate Results of Instructions Executed by Said Processors: no construction necessary at this time
It is so ORDERED.
BY THE COURT:
____________
PHILIP A. BRIMMER
United States District Judge