Ex Parte Tesch

Patent Trial and Appeal Board

Jun 13, 2018

14038127 (P.T.A.B. Jun. 13, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/038,127 09/26/2013
27820 7590 06/15/2018
WITHROW & TERRANOVA, P.L.L.C.
106 Pinedale Springs Way
Cary, NC 27511
FIRST NAMED INVENTOR
Bruce J. Tesch
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2867-1540 4521
EXAMINER
CLARK, CHRISTOPHER JAY
ART UNIT PAPER NUMBER
2836
NOTIFICATION DATE DELIVERY MODE
06/15/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@wt-ip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRUCE J. TESCH
Appeal2017-008552
Application 14/038,127 1
Technology Center 2800
Before BRIAND. RANGE, JENNIFER R. GUPTA, and
DEBRA L. DENNETT, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
SUMMARY
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
decision rejecting claims 1, 3-11, and 13-20. We have jurisdiction under 35
U.S.C. § 6(b ).
We AFFIRM.
1 Appellant is the Applicant, TriQuint Semiconductor, Inc. The Appeal
Brief states that the real party in interest is Qorvo US, Inc. Appeal Br. 2.
Appeal2017-008552
Application 14/038,127
STATEMENT OF THE CASE2
Appellant describes the invention as relating to electrostatic discharge
(ESD) circuitry for integrated circuits. Spec. ,r 1. Appellant's circuitry
seeks to provide "stable ESD protection with reduced in-rush current for a
fast-rising supply .... " Id. at 2.
Claim 1, reproduced below with emphases added to certain key
recitations, is illustrative of the claimed subject matter:
1. Electrostatic discharge (ESD) circuitry comprising:
a first node coupled with a supply voltage node and a
ground node;
a first transistor coupled with the first node and the supply
voltage node;
a second transistor coupled with the first node and the
ground node;
a second node coupled with the first transistor and the
second transistor;
a third transistor coupled with the second node;
a third node coupled with the third transistor, wherein a
first time period to charge the first node is less than a second
time period to discharge the third node; and
a fourth transistor coupled with the third node, wherein the
second time period to discharge the third node begins when
the third transistor is set to an off-state and ends when the
fourth transistor is set to an on-state.
2 In this Decision, we refer to the Final Office Action dated April 4, 2016
("Final Act."), the Appeal Brief filed November 30, 2016 ("Appeal Br."),
the Examiner's Answer dated March 23, 2017 ("Ans."), and the Reply Brief
filed May 23, 2017 ("Reply Br.").
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Appeal2017-008552
Application 14/038,127
Appeal Br. 19 (Claims App.). An embodiment of claim 1 is illustrated by
Figure 2 of the Specification which is reproduced below.
Figure 2 schematically illustrates ESD circuitry according to an embodiment
of the Specification.
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Miller et al.
("Miller")
Chen et al.
("Chen")
Traynor et al.
("Traynor")
Yeh et al.
("Yeh")
us 5,946,177
US 6,496,341 B 1
US 7,545,614 B2
US 2010/0149703 Al
3
Aug.31, 1999
Dec. 17, 2002
June 9, 2009
June 17, 2010
Appeal2017-008552
Application 14/038,127
REJECTIONS
The Examiner maintains the following rejections on appeal:
Rejection 1. Claims 1, 3-9, 11, and 13-19 under 35 U.S.C. § 103 as
unpatentable over Miller in view of Traynor. Final Act. 4.
Rejection 2. Claim 10 under 35 U.S.C. § 103 as unpatentable over
Miller in view of Traynor and further in view of Chen. Id. at 8.
Rejection 3. Claim 20 under 35 U.S.C. § 103 as unpatentable over
Miller in view of Traynor and Yeh. Id.
ANALYSIS
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) ("[I]t
has long been the Board's practice to require an applicant to identify the
alleged error in the examiner's rejections."). After considering the evidence
presented in this Appeal and each of Appellant's arguments, we are not
persuaded that Appellant identifies reversible error. Thus, we affirm the
Examiner's rejections for the reasons expressed in the Final Office Action
and the Answer. We add the following primarily for emphasis.
Rejection 1, claims 1, 3, 4, 8, 9, 11, 13, 14, 18, and 19.
The Examiner rejects claims 1, 3-9, 11, and 13-19 under 35 U.S.C.
§ 103 as unpatentable over Miller in view of Traynor. Final Act. 4.
Appellant presents an argument for claim 1 but does not present a separate
argument for claims 3, 4, 8, 9, 11, 13, 14, 18, or 19. Appeal Br. 9-13. We
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Appeal2017-008552
Application 14/038,127
therefore limit our discussion to claim 1. Claims 3, 4, 8, 9, 11, 13, 14, 18,
and 19 stand or fall with that claim. 37 C.F.R. § 4I.37(c)(l)(iv) (2013).
The Examiner finds that Miller teaches an ESD circuit with most of
the recitations of claim 1. Final Act. 4--5. The Examiner finds that Traynor
teaches a similar ESD circuit that additionally includes a fourth
transistor 118 that turns off clamping transistor 120 when the RC voltage at
RCoN dissipates. Id. at 5. The Examiner finds that Traynor teaches that its
additional circuitry "provides enhanced protection against subsequent ESD
events in comparison to the ESD protection taught by Miller" and concludes
that it would have been obvious to include Traynor's circuitry with the ESD
circuitry of Miller in order to gain this additional protection. Id. at 5---6.
We begin our analysis of Appellant's argument with claim
construction. Appellant argues that neither Miller nor Traynor teach the
"wherein the second time period to discharge the third node begins when the
third transistor is set to an off-state and ends when the fourth transistor is set
to an on-state" recitation of claim 1. Appeal Br. 10. In particular, Appellant
argues that turning on "clamp-tum off transistor 118" of Traynor "does not
signal the end of the discharge of the RCon node of Traynor." Reply Br. 4.
Thus, we understand Appellant's position to be that claim 1 's recitation of
"wherein the second time period to discharge the third node ... ends when
the fourth transistor is set to an on-state" requires that the fourth transistor
will not tum on until after the third node is discharged. In contrast, the
Examiner interprets the "second time period" as not being "defined by the
third node being discharged completely." Ans. 4.
During prosecution, claims are given their broadest reasonable scope
consistent with the specification. See, e.g., In re Am. Acad. of Sci. Tech.
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Appeal2017-008552
Application 14/038,127
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Here, claim 1 defines the "first
time period" based on the first time period being less than "a second time
period to discharge the third node." Claim 1 also states that the second time
period is a period "to discharge the third node [i.e., n3 in Figure 2 above]."
The claim states that the time period begins when the third transistor (M3 in
Figure 2) is set to an off-state. This makes sense because while M3 is on,
current flowing from source (VDD) to ground (GND) will be charging
capacitor C2 as it flows across resistor R2. Spec. Fig. 2. The capacitor C2
will begin discharging once M3 is switched off.
The claim also states that the second time period "ends when the
fourth transistor is set to an on-state." The Specification indicates that the
fourth transistor (M4) is switched on at "normal power up" but does not
indicate that the fourth node n3 must be completely discharged prior to M4
switching on. Rather, the Specification, like claim 1, indicates that the end
of the second time period may be defined by the fourth transistor turning on.
Spec. ,r 31 ("The second time period ... may end when the fourth transistor
M4 is set to an on-state (normal power-up)."). Given this context, we agree
with the Examiner that the end of the second time period of claim 1 is
defined by the fourth transistor being set by an on-state. Ans. 4. Thus, the
third node need not be discharged completely when the second time period
ends. Rather, the second time period ends whenever the fourth transistor is
set to an on-state.
With this claim construction in mind, we tum to the merits of
Appellant's argument. Figure 3 of Traynor is reproduced below.
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Application 14/038,127
l .... -RC
l
FIG . . J
Figure 3 illustrates an exemplary circuit diagram of an electrostatic
discharge protection circuit in accordance with an embodiment of Traynor.
Traynor 3 :34--36.
RC (resistor/capacitor) circuit including 108, 110, and the RCoN node
of Traynor is akin to RC circuit R2, C2, and n3 in Appellant's Figure 2. The
Examiner finds that voltage at Traynor' s RCoN ( mapped to the third node of
claim 3) will not be able to discharge until PMOS transistor 106 (mapped to
the third transistor of claim 1) is turned off. Ans. 3. The Examiner's finding
is supported by a preponderance of the evidence. As illustrated by Traynor' s
Figure 3, if transistor 106 is on, charge will flow from source (VDDE) to
ground (Vss)through resistor 108. Because of the resistor 108, capacitor
110 and corresponding node RCoN will remain charged. Once transistor 106
is turned off (i.e., during a normal power on event), capacitor 110 will begin
to discharge through resistor 108. Traynor 5:33-58. In this regard,
Traynor's circuit behaves similarly to that of Figure 2 of the Specification.
The Examiner finds that when the voltage at RCoN dissipates to below
an extra low switching point, inverter 114 is activated to tum on the fourth
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Appeal2017-008552
Application 14/038,127
transistor 118. Ans. 3. This finding is also supported by a preponderance of
the evidence. In particular, Traynor explains that transistor 118 begins to
conduct when a "predetermined voltage" is reached while voltage at RCoN is
diminishing. Traynor 5:33-58. While Appellant may be correct that
"turning on of the 'claim-tum off transistor 118' does not signal the end of
the discharge of the RCoN node of Traynor" (Reply Br. 4 ), this argument is
not persuasive, given a proper construction of claim 1. Claim 1 does not
require that RCoN be completely discharged prior to the end of the second
time period. Rather, the second time period ends when the fourth transistor
is set to an on-state.
Moreover, a preponderance of the evidence does not support
Appellant's argument that "the 'clamp-tum off transistor 118' of Traynor is
not involved with the discharge of the RCoN node." Reply Br. 4. Rather,
transistor 120 stays on for a long period of time to allow quick and full
dissipation of an ESD event (i.e., full dissipation of the RCoNnode).
Traynor 5:59-6:3. Transistor 118 turns off transistor 120 once it is no
longer needed (i.e., once the charge at RCoN is below a predetermined
voltage). Thus, activation of transistor 118 relates to discharge of the third
node as recited in claim 1. Much like Appellant's transistor M4,
transistor 118 activates once the ESD event dissipates to some degree so that
the device can return to normal operation.
Because Appellant's argument does not identify reversible error in the
Examiner's rejection, we sustain the Examiner's rejection of claims 1, 3, 4,
8, 9, 11, 13, 14, 18, and 19.
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Application 14/038,127
Rejection 1, claims 5 and 15.
Appellant argues claims 5 and 15 as a group. Appeal Br. 13-15. We
therefore limit our discussion to claim 5. Claim 15 stands or falls with
claim 5.
Claim 5 depends from claim 1 and recites additional transistors as
well as a latch node. Appeal Br. 20 (Claims App.). The Examiner finds that
Traynor discloses the recitations of claim 5. Final Act. 7. For example, the
Examiner finds that inverter 114 of Traynor comprises a sixth and seventh
transistor and that the drains of the sixth and seventh transistor "are []
connected to the gate of the fourth transistor 118 at a latch node." Id.; see
also Ans. 4--5.
Appellant argues that neither Miller nor Traynor suggest adding
Traynor's inverter 114 to Miller. Appeal Br. 13-15; Reply Br. 6. The
Examiner, however, determines that it would have been obvious to include
"the additional circuitry" of Traynor with Miller in order to provide
enhanced protection against subsequent ESD events. Final Act. 6.
Appellant presents no persuasive argument disputing the Examiner's stated
rationale as to why a person of ordinary skill in the art would have combined
the teachings of Miller and Traynor.
Appellant also argues that there would be no reason to combine
inverter 114 of Traynor with transistor 195 of Miller because they are each
"used for totally different purposes." Appeal Br. 14. Appellant's argument
does not persuasively identify error because it does not explain what the
"totally different purposes" are or why the combination would not provide
enhanced ESD protection as determined by the Examiner.
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Application 14/038,127
Appellant further argues that "the Final Office Action does not state
what is alleged to be claimed 'latch node.'" Reply Br. 7. As explained
above, the Examiner provides an explanation of why a latch node is taught
in the art. Final Act. 7; Ans. 4--5.
Because Appellant's arguments do not identify reversible error, we
sustain the Examiner's rejection of claims 5 and 15.
Rejection 1, claims 6, 7, 16, and 17.
Claims 6, 7, 16, and 17 each add recitations concerning the length of
the first time period relative to the second time period. The Examiner
provides findings establishing that the time constant of the second RC circuit
will be much longer than the few nanoseconds for charging the first node
during an ESD event. Ans. 5. The Examiner provides an explanation as to
why these teachings of Miller render obvious the recitations of claims 6, 7,
16, and 17. Id. Appellant does not persuasively rebut to the Examiner's
stated rationale and therefore does not identify reversible error. Appeal
Br. 15; Reply Br. 8 (merely copying and pasting argument from Appeal
Brief rather than addressing rationale provided in Answer). Because
Appellant does not persuasively identify reversible error, we sustain the
rejection of these claims.
Rejection 2, claim 10.
Claim 10 recites, "[t]he ESD circuitry of claim 1, wherein the third
transistor is a triple-well transistor or a silicon-on-insulator (SOI) transistor."
Appeal Br. 20 (Claims App.). The Examiner rejects claim 10 under
35 U.S.C. § 103 as unpatentable over Miller in view of Traynor and further
in view of Chen. Final Act. 8. The Examiner finds that applying SOI
technology to integrated circuits allows them to consume less power and
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Application 14/038,127
have higher operating speed. Id. The Examiner determines that it would
have been obvious to implement the Miller/Traynor combination using SOI
technology to gain this advantage. Id.; see also Ans. 5---6.
Appellant argues that Chen does not suggest using SOI for a third
transistor of ESD circuitry. Appeal Br. 16. Appellant also argues that the
purpose of using SOI is not the same as that stated by the Examiner. Id.
Appellant's argument does not, however, persuasively dispute the
Examiner's stated rationale as to why it would have been obvious to
combine the SOI teachings of Chen with the Miller/Traynor combination.
See Reply Br. 8-9 ( copying and pasting from Appeal Brief rather than
addressing the Examiner's position stated in the Answer). The Examiner's
stated reason to combine references does not need to be the same as the
advantage recognized by Appellant. Ex parte Obiaya, 227 USPQ 58, 60
(BPAI 1985). We sustain this rejection.
Rejection 3, claim 20.
Appellant presents the same argument discussed above with respect to
claim 1. Appeal Br. 17. That argument does not identify reversible error for
the reasons explained above, and we sustain this rejection.
DECISION
For the above reasons, we affirm the Examiner's rejections of
claims 1, 3-11, and 13-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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