Ex Parte Pagani

Patent Trial and Appeal Board

Jul 18, 2017

13801354 (P.T.A.B. Jul. 18, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/801,354 03/13/2013 Alberto PAGANI 11AG0691US01/140650-1019 5274
117381 7590 07/20/2017
GWS-ST-EP
Gardere Wynne Sewell LLP
Intellectual Property Section
2021 MCKINNEY AVE., SUITE 1600
DALLAS, TX 75201-2237
EXAMINER
GARCES, NELSON Y
ART UNIT PAPER NUMBER
2814
NOTIFICATION DATE DELIVERY MODE
07/20/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipgws @ gardere. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ALBERTO PAGANI
(Applicant: STMICROELECTRONICS S.R.L.)
Appeal 2016-007909
Application 13/801,354
Technology Center 2800
Before ROMULO H. DELMENDO, JULIA HEANEY, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
CASHION, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134 from a final rejection of
claims 21—26, 28—30, 33—35 and 42-45. We have jurisdiction under
35 U.S.C. § 6.
We AFFIRM-IN-PART.
Appeal 2016-007909
Application 13/801,354
Claims 21 and 33 are illustrative of the subject matter on appeal and
are reproduced below:
21. An integrated circuit, comprising:
an integrated circuit substrate having a peripheral side surface;
a metallization layer mounted to the integrated circuit substrate;
a dielectric layer having a uniform thickness and disposed in contact
with a top surface of the metallization layer and disposed in contact with
both a peripheral side surface of the metallization layer and the peripheral
side surface of the integrated circuit substrate;
wherein said dielectric layer includes:
a first communication pad disposed along a first face of the
dielectric layer and electrically connected to the metallization layer; and
a second communication pad disposed along a second face of
the dielectric layer and electrically connected to the metallization layer.
33. A system, comprising:
a first integrated circuit, including:
a first integrated circuit die;
a first metallization layer mounted to a top surface of the first
integrated circuit die;
a first dielectric layer having a first side portion disposed in
contact with a peripheral side surface of both the first integrated circuit die
and the first metallization layer and further having a first non-side portion
disposed in contact with a top surface of the first metallization layer, and
a first communication pad disposed along the first side portion;
and
a second integrated circuit, including:
a second integrated circuit die;
a second metallization layer mounted to a top surface of the
second integrated circuit die;
a second dielectric layer having a second side portion disposed
in contact with a peripheral side surface of both the second integrated circuit
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Application 13/801,354
die and the second metallization layer that is facing the first side portion and
further having a second non-side portion disposed in contact with a top
surface of the second metallization layer, and
a second communication pad disposed along the second side
portion and coupled to the first communication pad.
Appellant requests review of the Examiner’s rejection of claims 21—
26, 28—30, 33—35 and 42-45 under 35 U.S.C. § 102(b) as anticipated by
Bartilson (US 6,172,874 Bl, issued January 9, 2001). Final Act. 3; App. Br.
6.
OPINION
After review of the respective positions provided by Appellant and the
Examiner, we REVERSE the Examiner’s prior art rejection of claims 33—35
under 35 U.S.C. § 102(b) for the reasons presented by Appellant. However,
we AFFIRM the Examiner’s prior art rejection of claims 21—26, 28—30 and
42-45 for the reasons presented by the Examiner. Our reasoning follows.
Claims 33—351
We REVERSE.
Claim 33 is directed to a system comprising two integrated circuits
having their respective integrated circuit dies arranged by coupling together
the side contact pads located on the periphery side surfaces of the respective
dies.
We refer to the Examiner’s Final Action for a statement of the
rejection of independent claim 33. Final Act. 6—7.
1 We limit our discussion to independent claim 33.
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Application 13/801,354
Appellant argues the language of claim 33 requires a specific order
for the integrated circuits that results in horizontal communication enabled
by the contact pads associated with the side portions of the dielectric layers
applied to the two different integrated circuits where the dielectric layers
face each other. App. Br. 13—14. According to Appellant, Bartilson
discloses that the flaps of the flexible circuit of each chip assembly are
vertically stacked to be parallel to each other without the sides facing each
other as claimed. App. Br. 14; Bartilson Figure 5.
We agree with Appellant. The Examiner relies on Bartilson’s
description of the individual chip module as a building block for a complete
computing unit as descriptive of the claimed arrangement of the first and
second integrated circuits. Final Act. 7; Bartilson col. 6,11. 24—15, col. 8,11.
46—67, col. 9,11. 1—6. However, the Examiner has not directed us to any
portion of Bartilson that describes a system comprising two integrated
circuits arranged having the side contact pads facing each other and coupled
as claimed. Thus, we agree with Appellant that the Examiner has not
adequately explained how Bartilson anticipates the subject matter of claims
33—35. App. Br. 8.
Accordingly, we reverse the Examiner’s prior art anticipatory
rejection of claims 33—35 for the reasons presented by Appellant and given
above.
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Application 13/801,354
Claims 21—26, 28—30, and 42—452
We AFFIRM.
Claim 21
Independent claim 21 is directed to an integrated circuit having an
integrated circuit substrate with a metallization layer mounted on top and
further comprising a dielectric layer in contact with the metallization layer
and the peripheral sides of the metallization layer and the substrate. Claim
21 further requires that the dielectric layer includes first and second
communication pads along the dielectric layer portion contacting the
metallization layer and along the dielectric layer portion contacting the
peripheral sides of the assembly.
The Examiner finds Bartilson describes an integrated circuit
comprising an integrated circuit substrate 306 having metallization layers
700 and a dielectric layer 206 mounted over the metallization layers. Final
Act. 3; Ans. 4; Bartilson Figures 6—7, col. 6,11. 24—38. The Examiner also
finds Bartilson describes dielectric layer 206 includes flaps 220, 222, and
224 having communication pads 221, 222, 223, respectively. Final Act. 3;
Ans. 4; Bartilson Figures 6—7, col. 6,11. 24-46. Dielectric layer 206 further
2 Appellant presents arguments addressing the rejection of independent
claim 21. See generally Appeal Brief. In addressing the rejection of
independent claim 42, Appellant relies on the arguments presented when
discussing claim 21 and also presents additional arguments. Id. at 15—16.
Appellant does not present additional arguments for the dependent claims.
See generally Appeal Brief. Accordingly, we focus our discussion
principally on claim 21 with the understanding that it also applies to
independent claim 42. We address the additional arguments for claim 42
separately. Dependent claims 22—26, 28—30, and 43 45 stand or fall with
claims 21 and 42.
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comprises a flat portion 210 adjacent the flaps 220, 222, and 224, the flat
portion 210 additionally comprising communication pads 212. Bartilson
Figures 6—7, col. 6,11. 24-46. The Examiner finds that flaps 220, 222 and
224 contact the peripheral sides of the integrated circuit 306 once flipped
towards those sides. Ans. 5; Bartilson Figure 8. Thus, the Examiner
determines that the structure of Bartilson’s Figure 6 anticipates the subject
matter of claim 21. Final Act. 3; Ans. 6.
Appellant argues the elements of Bartilson are not arranged as recited
in claim 21 because Bartilson uses flexible circuits with peripheral sides that
are spaced apart from the chips and that extend beyond the chips for the
purpose of using the flexible circuits to enable the chips to be stacked
vertically for connection to printed circuit boards. App. Br. 8—9; Bartilson
Figure 3, col. 2, 11. 20—23. With respect to the embodiment in Figure 6 of
Bartilson, Appellant contends Bartilson only discloses the pads 212 on the
flat portion of the chip 306 are attached to the flexible circuit via solder bath,
adhesive attachment, or compliant attachment but does not disclose that any
part of the peripheral edge surface of the chip 306 is attached to the flaps of
the flexible circuit. App. Br. 9; Bartilson Figures 2—7, col. 6,11. 53—65.
Thus, Appellant argues there is no disclosure in Bartilson that any part of a
peripheral side edge of the chip contacts the flap portions of the flexible
circuit. App. Br. 9.
We are unpersuaded by these arguments. In order to anticipate, a
reference must identify something falling within the claimed subject matter
with sufficient specificity to constitute a description thereof within the
purview of § 102. In re Schaumann, 572 F.2d 312, 317 (CCPA 1978). ft is
well established that specific examples of the claimed subject matter are not
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Application 13/801,354
necessary to establish anticipation. Rather, to anticipate, one skilled in the
art must be able to “at once envisage” the claimed subject matter in the prior
art disclosure. In re Petering, 301 F.2d 676, 681 (CCPA 1962). Further, in
evaluating references, it is proper to take into account not only the specific
teachings of the references but also the inferences which one skilled in the
art would reasonably be expected to draw therefrom. In re Preda, 401 F.2d
825, 826 (CCPA 1968) (it is well established that in evaluating references it
is proper to take into account not only the specific teachings of the
references but also the inferences which one skilled in the art would
reasonably be expected to draw therefrom).
Figure 6 of Bartilson shows the four comers of the integrated circuit
substrate 306 aligned with the four comers of the flat portion 210 of the
dielectric layer 206. Thus, one skilled in the art would infer from Bartilson’s
Figure 6 that integrated circuit 306 and flat portion 210 of the dielectric layer
206 are coextensive with each other. Based on this inference, we agree with
the Examiner’s finding that flaps 220, 222 and 224 would contact the
peripheral sides of the integrated chip substrate 306 once flipped towards
these sides. Ans. 5—6.
Appellant further argues Bartilson does not disclose, teach, or suggest
a dielectric layer disposed in contact with both a peripheral side surface of
the metallization layer and the peripheral side surface of the integrated
circuit substrate. Id. at 11.
We are also unpersuaded by this argument. As noted by the
Examiner, Bartilson discloses the communication pads (metallization layers)
of the dielectric layer 206 can be changed to any corresponding pattern of
pads on the circuit module 306. Ans. 4—5; Bartilson col. 6,11. 47—59. One
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skilled in the art would infer from this disclosure that, although not depicted
in Figure 6, the sides of integrated chip 306 could have communication pads.
See Preda, 401 F.2d at 826. Thus, in such a circumstance, the Examiner
demonstrated a reasonable basis that flaps 220, 222 and 224 would also
contact the peripheral sides of the metallization layer once flipped towards
these sides. Ans. 4—5. Appellant’s arguments fail to consider the prior art as
a whole. Therefore, Appellant’s arguments are not persuasive of reversible
error in the Examiner’s finding that Bartilson anticipates claim 21.
Claim 42
With respect to claim 42, Appellant additionally argues the subject
matter of this claim requires the use of a substrate die as opposed to the more
general recitation of an integrated circuit substrate of Claim 21. App. Br. 13,
15-16.
We are unpersuaded by this argument. Appellant does not adequately
explain the difference between a substrate die and an integrated circuit
substrate or how this distinguishes the claimed invention from the integrated
circuit device of Bartilson. In fact, Appellant’s statement that the phrase
“integrated circuit substrate” is a general recitation would infer to one skilled
in the art that the phrase “integrated circuit substrate” is inclusive of a
substrate die. Therefore, Appellant has not adequately explained error in the
Examiner’s assertion that the terms are used interchangeably. Ans. 6.
Accordingly, we affirm the Examiner’s prior art rejection of claims
21—26, 28—30 and 42-45 under 35 U.S.C. § 102(b) for the reasons presented
by the Examiner and given above.
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We note that Appellant presented arguments for the first time in the
Reply Brief filed August 12, 2016 in furtherance of their assertion that the
flaps 220, 222, and 224 shown in Bartilson’s Figure 6 do not contact the
peripheral edges of the integrated surface 306 (Reply Br. 2—5), and
concerning the Examiner’s assertion that the terms “integrated circuit
substrate” and “substrate die” are interchangeable. Id. at 8—9. Any
argument not presented in the Appeal Brief will not be considered when
filed in a Reply Brief, absent a showing of good cause explaining why the
argument could not have been presented in the Appeal Brief. See Ex parte
Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (informative) (“[T]he reply
brief [is not] an opportunity to make arguments that could have been made
during prosecution, but were not. Nor is the reply brief an opportunity to
make arguments that could have been made in the principal brief on appeal
to rebut the Examiner’s rejections, but were not.”); see also 37 C.F.R. §
41.41(b)(2). Appellant has not shown good cause why this argument should
now be considered.
ORDER
The Examiner’s prior art rejection of claims 33—35 under 35 U.S.C.
§ 102(b) is reversed.
The Examiner’s prior art rejections of claims 21—26, 28—30 and 42-45
under 35 U.S.C. § 102(b) are affirmed.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
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AFFIRMED-IN-PART
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