Ex Parte Gopal

Patent Trial and Appeal Board

Aug 22, 2016

13687896 (P.T.A.B. Aug. 22, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/687,896 11128/2012
65913 7590 08/24/2016
Intellectual Property and Licensing
NXPB.V.
411 East Plumeria Drive, MS41
SAN JOSE, CA 95134
FIRST NAMED INVENTOR
KiranGOPAL
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
81421140US04 1434
EXAMINER
KIM,TIJNGH
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
08/24/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KIRAN GOP AL
Appeal2015-000484
Application 13/687,896
Technology Center 2800
Before: LARRY J. HUME, NORMAN H. BEAMER, and
JOHN R. KENNY, Administrative Patent Judges.
KENNY, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF CASE
This is an appeal under 35 U.S.C. § 134 from a rejection of
claims 1-5, 7, and 8. Claim 6 is objected as being dependent upon a rejected
base claim. 1 (Final Act. 6.) We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 Claims 9-12 were withdrawn from consideration during prosecution.
(Final Act. 1.)
Appeal2015-000484
Application 13/687,896
INVENTION
The disclosed and claimed invention is directed to a glitch filter
circuit. Claim 1, reproduced below, is illustrative of the claimed subject
matter (emphases added to contested limitations):
1. A glitch filter circuit comprising:
an input circuit having a first input and a second input,
wherein the input circuit is configured to detect both rising and
falling signal level transitions of an input signal at the first input;
an RC delay circuit at an output of the input circuit;
an output circuit coupled to an output of the RC delay
circuit, wherein the output circuit is configured to toggle an
output of the glitch filter circuit between high and low levels in
response to the RC delay circuit output; and
a feedback path from the output circuit to the second input
of the input circuit, wherein the input signal enters the glitch
filter only at the first input.
RFJECTION
Claims 1-5, 7, and 8 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Sakhuja et al.(US 4,471,235; iss. Sep. 11, 1984) ("Sakhuja"). 2
ISSUES
Appellant raises the issues of whether Sakhuja discloses: (i) the input-
signal-entry limitation ("wherein the input signal enters the glitch filter only
at the first input") and (ii) the RC-delay-circuit limitation ("an RC delay
circuit at an output of the input circuit") of claim 1. (App. Br. 4, Reply
Br. 2.)
2 The Examiner withdrew the rejection of claims 1-8 for indefiniteness
under 35 U.S.C. § 112, second paragraph. (Ans. 2.)
2
Appeal2015-000484
Application 13/687,896
ANALYSIS
For the first issue, the Examiner finds the signal entering input 40 in
Sakhuja satisfies the input-signal-entry limitation of claim 1. (Ans. 2.)
Appellant argues the Examiner erred because Sakhuja has more than one
input. (App. Br. 4; Reply Br. 2.) We are not persuaded by this argument
because Appellant is arguing limitations not recited in the claim. The input-
signal-entry limitation does not require that the glitch circuit have only one
input. Claim 1 itself recites a second input. (See claim 1.) The input-signal-
entry limitation merely requires that the "input signal at the first input"
"enters the glitch filter only at the first input." As the Examiner finds, and as
Figure 4 of Sakhuja illustrates, the input signal at input 40 enters Sakhuja's
circuit only at input 40. (Ans. 2, Sakhuja Fig. 4.) Therefore, in agreement
with the Examiner, we find the input signal at input 40 satisfies the input-
signal-entry limitation.
For the second issue, the Examiner finds that RC network 49 in
Sakhuja satisfies the RC delay circuit limitation. (Ans. 3) Appellant argues
the Examiner erred because (a) RC network 49 is coupled between Vee and
ground and (b) input circuit 32 sends a signal to XNOR 33, which flows into
Schmitt trigger inverter 34. (App. Br. 4; Reply Br. 2-3.) We are not
persuaded by these arguments, as they are not commensurate with the scope
of the claim.
The RC-delay-circuit limitation does not preclude coupling the RC
network between Vee and ground or preclude input circuit 32 from sending a
signal to XNOR 33, which flows into Schmitt trigger inverter 34. (See
claim 1.) The only connection that the limitation requires is that the RC
delay circuit be at an output of the input circuit, and Figure 4 depicts RC
3
Appeal2015-000484
Application 13/687,896
network 49 as being connected to output 44 of the input circuit (NAND gate
32 and exclusive NOR gate 33). (Id; Ans. 3; Sakhuja Fig. 4)
The Examiner sets forth how RC network 49 operates as an RC delay
circuit, and Appellant presents no persuasive evidence or arguments
contradicting that showing by the Examiner. (App. Br. 4; Ans. 2-3; Reply
Br. 2-3.) Accordingly, we agree with the Examiner that RC network 49
satisfies the RC-delay circuit limitation, and we adopt the Examiner's
findings and rationales regarding the RC-network and input-signal-entry
limitations. (Final Act. 4---6; Ans. 2-3.)
Therefore, we sustain the rejection of claim 1 and of claims 2-5, 7,
and 8, not separately argued.
DECISION
We affirm the rejection of claims 1-5, 7, and 8.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
4