Ex Parte Cho et al

Patent Trial and Appeal Board

Oct 31, 2012

10886168 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/886,168 07/07/2004 Sang-yeun Cho 5649-1269 5410
20792 7590 10/31/2012
MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH, NC 27627
EXAMINER
YU, JAE UN
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
10/31/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte SANG-YEUN CHO and WOO-YOUNG JUNG
____________________

Appeal 2010-001462
Application 10/886,168
Technology Center 2100
____________________

Before: JOSEPH L. DIXON, CARLA M. KRIVAK, and
JAMES R. HUGHES, Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-001462
Application 10/886,168

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a final rejection of
claims 1, 2, 4, 9, 10, 12-14, and 17-23. The § 103(a) rejection for claims 3,
5, 6, and 11 has been withdrawn by the Examiner. (Ans. 2-3). We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

The claims are directed to cache memory systems having a flexible
buffer memory portion and methods of operating the same. Claim 1,
reproduced below, is representative of the claimed subject matter:
1. A cache memory system, comprising:
a processor;
a cache memory that comprises a first memory portion
and a flexible buffer memory portion, the cache memory being
configured to store data therein independent of a data type; and
a cache controller that is coupled to the cache memory
and is configured to control allocation and/or deallocation of
blocks from the first memory portion to and/or from the flexible
buffer memory portion based on a mode and/or an index
address;
wherein a location of a part of the first memory portion
corresponds to an index or offset address of the processor
stored in a part of the processor.

REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Leary
Wu
Krishnamurthy
Creta
US 5,301,295
US 5,668,968
US 6,157,987
US 7,089,362 B2
Apr. 5, 1994
Sep. 16, 1997
Dec. 5, 2000
Aug. 8, 2006
Appeal 2010-001462
Application 10/886,168

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REJECTIONS
Claims 1, 2, 12, 13, and 17-20 stand rejected under 35 U.S.C §103(a)
as being unpatentable over Krishnamurthy and Wu. (Ans. 4-7).
Claims 4 and 14 stand rejected under 35 U.S.C §103(a) as being
unpatentable over Krishnamurthy, Wu, and Creta. (Ans. 7-8).
Claims 9, 10, 21, and 22 stand rejected under 35 U.S.C §103(a) as
being unpatentable over Krishnamurthy, Leary, and Wu. (Ans. 8-11).
Claim 23 stands rejected under 35 U.S.C §103(a) as being
unpatentable over Krishnamurthy, Leary, Wu, and Creta. (Ans. 11-12).

ANALYSIS
With respect to representative claim 1, Appellants argue a
differentiation of the teachings of figure 3 of the Krishnamurthy reference.
(App. Br. 7; Reply Br. 2). The Examiner identifies that the express features
of Krishnamurthy relied on by Appellants in the arguments are not found in
the language of independent claim 1. (Ans. 4-5). Therefore, Appellants did
not demonstrate error in the Examiner's showing of obviousness. Rather, we
agree with the Examiner's application of the prior art teachings of
Krishnamurthy in view of Wu. (Ans. 4-5). We further find that Appellants'
arguments go beyond the Examiner's application of the prior art teachings of
Krishnamurthy in the Answer. The Examiner maintains that Krishnamurthy
teaches:
"a cache memory that comprises a first memory portion ["line
buffers" allocated for pixel information and Z information,
Column 8, Lines 23-29] and a flexible buffer memory portion
["line buffers" allocated for texel information, Column 8, Lines
23-29], the cache memory being configured to store data therein
independent of a data type [Column 8, Lines 23- 29]" and "A
Appeal 2010-001462
Application 10/886,168

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cache controller ["LRU management circuitry", Column 8,
Lines 23-29] that is coupled to the cache memory and is
configured to control allocation and/or deallocation of blocks
from the first memory portion to and/or from the flexible buffer
memory portion based on a mode and/or an index address
[Allocating all line buffers for texel information in "texel only
mode", Column 8, Lines 23-29]".

(Ans. 4) (emphasis omitted). We agree with the Examiner's application of
the prior art teachings and find them to be based upon a broad but reasonable
interpretation of the claimed invention. We find the remainder of
Appellants’ arguments go beyond the express language of the claims as
maintained by the Examiner. (Ans. 12-14). Therefore, Appellants'
arguments do not indicate error in the Examiner's showing of obviousness of
representative independent claim 1. Thus, we sustain the rejections of
claims 1 and 12 and dependent claims 2, 13, and 17-20.
With respect to independent claims 9 and 21, Appellants rely upon the
same arguments advanced with respect to claims 1 and 12. (App. Br. 9-10).
Since we find those arguments unpersuasive of error, we similarly find no
error in the Examiner's showing of obviousness of claims 9, 10, and 21- 23.
With respect to dependent claims 4, 14, and 23, Appellants rely upon
the same arguments advanced with respect to claims 1, 9, 12, and 21. (App.
Br. 10). Since we find those arguments unpersuasive of error, we similarly
find no error in the Examiner's showing of obviousness of claims 4, 14, and
23.
Appeal 2010-001462
Application 10/886,168

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CONCLUSIONS OF LAW
The Examiner did not err in rejecting claims 1, 2, 4, 9, 10, 12-14, and
17-23 under obviousness.
DECISION
For the above reasons, the Examiner’s rejections of claims 1, 2, 4, 9,
10, 12-14, and 17-23 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2009).

AFFIRMED

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