Ex Parte Chen et al

Patent Trial and Appeal Board

Mar 27, 2017

13227965 (P.T.A.B. Mar. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/227,965 09/08/2011 GONG CHEN MT11451TP 6576
23125 7590 03/29/2017
NXP USA, Inc.
LAW DEPARTMENT
6501 William Cannon Drive West TX30/OE62
AUSTIN, TX 78735
EXAMINER
HARRISTON, WILLIAM A
ART UNIT PAPER NUMBER
2899
NOTIFICATION DATE DELIVERY MODE
03/29/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GONG CHEN and LINGHUI WU
Appeal 2016-002046
Application 13/227,965
Technology Center 2800
Before MARKNAGUMO, CHRISTOPHER L. OGDEN, and
JENNIFER R. GUPTA, Administrative Patent Judges.
GUPTA, Administrative Patent Judge.
DECISION ON APPEAL1
Appellants2 appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision finally rejecting claims 1, 2, 4, 5, 7, 8, and 10-20. We have
jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
1 In this decision, we refer to Appellants’ Specification filed
September 8, 2011, the Final Office Action mailed January 30, 2014 (“Final
Act.”), the Advisory Action mailed April 24, 2014 (“Advisory Act.), the
Appeal Brief filed July 7, 2014 (“App. Br.”), the Examiner’s Answer mailed
December 18, 2014 (“Ans.”), and the Reply Brief filed February 18, 2015
(“Reply Br.”).
2 Appellants identify the real party in interest as Freescale Semiconductor,
Inc. App. Br. 2.
Appeal 2016-002046
Application 13/227,965
The subject matter on appeal relates generally to semiconductor
contacts, and more specifically, to contacts for a non-volatile memory.
Spec. 11. Claim 1, reproduced below with some formatting added, is
illustrative of the claims on appeal.
1. A semiconductor device comprising:
a first non-volatile memory cell having a first gate stack;
a second non-volatile memory cell having a second gate
stack, wherein the first nonvolatile memory cell and the
second non-volatile memory cell share a source/drain region
that is between the first gate stack and the second gate stack;
and
an electrically conductive contact touching the source/drain
region and spaced from the first gate stack and the second gate
stack, wherein:
the contact has an oval cross-section touching and
contained within the source drain region and having a short
dimension and a long dimension;
the short dimension is along a shortest line between the
first gate stack and the second gate stack and the long
dimension is orthogonal to the shortest line between the first
gate stack and the second gate stack;
the first gate stack and the second gate stack are spaced
from the contact to reliably avoid touching the contact.
App. Br. 13 (Claims Appendix).
DISCUSSION
The Examiner maintains the rejection under 35 U.S.C. § 103(a) of
claims 1, 2, 4, 5, 7, 8, and 10—20 as unpatentable over Emden et al.
(US 2007/0263445 Al, published November 15, 2007, hereinafter “Emden”)
2
Appeal 2016-002046
Application 13/227,965
in view of Kim (US 2007/0269971 Al, published November 22, 2007,
hereinafter “Kim”). Final Act. 3—9.3
We will focus on representative independent claim 1 because it
contains the argued limitations.
The Examiner interprets “gate stack” as recited in claim 1 as “a gate
electrode in combination with a gate dielectric.” Advisory Act. 2; Ans. 3.
The Examiner finds that Emden’s Figure 3, reproduced below with
annotations, discloses a semiconductor device as in claim 1, except an
electronically conductive contact having
an oval cross-section touching and contained within the source
drain region and having a short dimension and a long dimension;
the short dimension is along a shortest line between the first gate
stack and the second gate stack and the long dimension is
orthogonal to the shortest line between the first gate stack and
the second gate stack.
Final Act. 3.
3 Although the Examiner has not explicitly indicated that the rejection under
35 U.S.C. § 112, second paragraph, of claim 13 for “insufficient antecedent
basis” has been withdrawn in the Answer (Final Act. 2; Ans. 2—6), in an
Amendment filed March 28, 2014, Appellants amended the recitation “the
active region” in line 6 of claim 13 to “an active region,” to correct the
antecedent basis issue raised by the Examiner. Thus, the Examiner’s § 112,
second paragraph rejection of claim 13 is moot.
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Appeal 2016-002046
Application 13/227,965
6 7 Il716 !e 7 17 16 6 7/ 17 10 6 7 15
11
Emden Figure 3, above, depicts a schematic side view of a non-volatile
memory cell array according to the invention described in Emden. The
Examiner finds that the gate stack in Emden’s Figure 3 comprises “a gate
dielectric 16 and a gate electrode 17.” Advisory Act. 2; see also Ans. 3.
Appellants argue that neither Emden nor Kim discloses a first non­
volatile memory cell having a first gate stack and a second non-volatile
memory cell having a second gate stack, as recited in independent claim 1.
App. Br. 8. Appellants’ argument hinges on the Examiner’s construction of
the term “gate stack.” Appellants’ contend that the Examiner’s
interpretation of the term “gate stack” is not consistent with the written
description of the claimed invention as set forth in the Specification. See id.
at 9. According to Appellants, their Specification uses the term “gate stack”
to refer to structures including a plurality of gate electrodes, rather than a
single gate electrode as disclosed in Emden. Id. (citing Spec. 112; Fig. 1 of
Appellants’ application).
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Appeal 2016-002046
Application 13/227,965
Appellants’ arguments are persuasive of reversible error in the
Examiner’s rejection of claim 1. Figure 1 of Appellants’ application is
reproduced below.
10-^
Figure 1, above, depicts a cross section of a semiconductor device according
to an embodiment as described in Appellants’ Specification. Paragraph 12
of Appellants’ Specification states that “Gate stack 14 [(e.g., first gate
stack)] includes a gate dielectric on substrate 12, a floating gate [40] on gate
dielectric 38, a dielectric layer 42 on floating gate 40, and a control
gate [44] on dielectric layer 42. (emphasis added).
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Appeal 2016-002046
Application 13/227,965
“While the Board must give the terms their broadest reasonable
construction, the construction cannot be divorced from the specification and
the record evidence.” In re NTP, Inc., 654 F.3d 1279, 1288 (Fed. Cir. 2011).
On this record, a preponderance of the evidence supports Appellants’
contention that the Examiner’s interpretation of the term “gate stack” is not
consistent with Appellants’ Specification as it would be interpreted by one
of ordinary skill in the art. The broadest reasonable interpretation consistent
with Appellants’ Specification (| 12; Fig. 1 of Appellants’ application), and
Appellants’ argument in their Appeal Brief, requires a “gate stack” as recited
in claim 1 to include a plurality of gate electrodes, not just a single gate
electrode as disclosed in Emden. Because the Examiner’s rejection is based
on a flawed claim construction of a disputed claim limitation, and the
Examiner has not identified any teaching or suggestion in Emden or Kim of
a non-volatile memory cell having a gate stack (i.e., a plurality of gate
electrodes), we cannot sustain the Examiner’s obviousness rejection of
claims 1, 2, 4, 5, 7, 8, and 10-20 over Emden and Kim.
DECISION
For the above reasons, the Examiner’s rejection of claims 1, 2, 4, 5, 7,
8, and 10-20 is reversed.
REVERSED
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